The recent Printed Wiring Board embedding technology is an attractive
packaging alternative that allows a very high degree of miniaturization by
stacking multiple layers of embedded chips. This disruptive technology will
further increase the thermal management challenges by concentrating heat
dissipation at the heart of the organic substrate structure. In order to
allow the electronic designer to early analyze the limits of the power
dissipation, depending on the embedded chip location inside the board, as
well as the thermal interactions with other buried chips or surface mounted
electronic components, an analytical thermal modelling approach was
established. The presented work describes the comparison of the analytical
model results with the numerical models of various embedded chips
configurations. The thermal behaviour predictions of the analytical model,
found to be within ?10% of relative error, demonstrate its relevance for
modelling high density electronic board. Besides the approach promotes a
practical solution to study the potential gain to conduct a part of heat flow
from the components towards a set of localized cooled board pads.