2 Gb/s operation of an optical-clock-driven monolithically integrated GaAs D-flip-flop with metal-semiconductor-metal photodetectors for high-speed synchronous circuits

1992 ◽  
Vol 4 (2) ◽  
pp. 160-162 ◽  
Author(s):  
S. Kawanishi ◽  
Y. Yamabayashi ◽  
T. Takada ◽  
H. Takara ◽  
M. Saruwatari ◽  
...  
Keyword(s):  
High Speed ◽  
Optical Clock ◽  
Flip Flop ◽  
Synchronous Circuits ◽  
Monolithically Integrated ◽  
Metal Semiconductor Metal

High‐speed monolithically integrated GaAs photoreceiver using a metal‐semiconductor‐metal photodiode

1985 ◽  
Vol 47 (11) ◽  
pp. 1129-1131 ◽  
Author(s):  
M. Ito ◽  
T. Kumai ◽  
H. Hamaguchi ◽  
M. Makiuchi ◽  
K. Nakai ◽  
...  
Keyword(s):  
High Speed ◽  
Monolithically Integrated ◽  
Metal Semiconductor Metal

High speed monolithically integrated metal-semiconductor-metal waveguide detector on InP

1990 ◽  
Author(s):  
J. B. D. SOOLE ◽  
H. SCHUMACHER ◽  
R. ESAGUI ◽  
H. P. LeBLANC ◽  
R. BHAT ◽  
...  
Keyword(s):  
High Speed ◽  
Monolithically Integrated ◽  
Metal Semiconductor Metal ◽  
Metal Waveguide

High-speed operation of resonant tunnelling flip-flop circuit employing MOBILE (monostable-bistable transition logic element)

1997 ◽  
Vol 33 (20) ◽  
pp. 1733 ◽  
Author(s):  
K. Maezawa ◽  
H. Matsuzaki ◽  
K. Arai ◽  
T. Otsuji ◽  
M. Yamamoto
Keyword(s):  
High Speed ◽  
Logic Element ◽  
Flip Flop ◽  
Resonant Tunnelling

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC

2021 ◽  
Author(s):  
Min-su Kim ◽  
Wonhyun Choi ◽  
Jong-Woo Kim ◽  
Chunghee Kim ◽  
Jae-Hyuk Oh ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Flop
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