An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

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A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2015.2463110 ◽

2015 ◽

Vol 50 (12) ◽

pp. 2891-2900 ◽

Cited By ~ 33

Author(s):

Martin J. Kramer ◽

Erwin Janssen ◽

Kostas Doris ◽

Boris Murmann

Keyword(s):

Sar Adc ◽

Input Buffer

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Design of a high sensitivity and low power ultrasound receiver with a high-resolution SAR ADC for photoacoustic sensing and imaging

10.32657/10356/144400 ◽

2020 ◽

Author(s):

◽

Chuanshi Yang

Keyword(s):

High Resolution ◽

Low Power ◽

High Sensitivity ◽

Sar Adc ◽

Power Ultrasound

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SAR ADC Algorithm With Redundancy Using Pseudo-Silver-Ratio

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.137.222 ◽

2017 ◽

Vol 137 (2) ◽

pp. 222-228

Author(s):

Yutaro Kobayashi ◽

Takuya Arafune ◽

Shohei Shibuya ◽

Haruo Kobayashi

Keyword(s):

Sar Adc

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An 11-Bit Single-Ended SAR ADC with an Inverter-Based Comparator for Design Automation

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.1331 ◽

2016 ◽

Vol E99.C (12) ◽

pp. 1331-1334 ◽

Cited By ~ 1

Author(s):

Guan-Wei JEN ◽

Wei-Liang LIN

Keyword(s):

Design Automation ◽

Sar Adc

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Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0089 ◽

2000 ◽

Author(s):

J. N. C. de Luna ◽

M. O. del Fierro ◽

J. L. Muñoz

Keyword(s):

Flash Memory ◽

Electromagnetic Interference ◽

Yield Loss ◽

High Amplitude ◽

Physical Analysis ◽

Input Buffer ◽

Automated Test Equipment ◽

Root Cause ◽

Root Cause Identification ◽

Test Process

Abstract An advanced flash bootblock device was exceeding current leakage specifications on certain pins. Physical analysis showed pinholes on the gate oxide of the n-channel transistor at the input buffer circuit of the affected pins. The fallout contributed ~1% to factory yield loss and was suspected to be caused by electrostatic discharge or ESD somewhere in the assembly and test process. Root cause investigation narrowed down the source to a charged core picker inside the automated test equipment handlers. By using an electromagnetic interference (EMI) locator, we were able to observe in real-time the high amplitude electromagnetic pulse created by this ESD event. Installing air ionizers inside the testers solved the problem.

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