A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier

With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.

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Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2015.2427931 ◽

2015 ◽

Vol 62 (7) ◽

pp. 1776-1784 ◽

Cited By ~ 13

Author(s):

Byungkyu Song ◽

Taehui Na ◽

Jisu Kim ◽

Jung Pill Kim ◽

Seung H. Kang ◽

...

Keyword(s):

Offset Cancellation ◽

Sense Amplifier ◽

Deep Submicrometer

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Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803052 ◽

2002 ◽

Vol 37 (10) ◽

pp. 1356-1360 ◽

Cited By ~ 14

Author(s):

Sanghoon Hong ◽

Sejun Kim ◽

Jae-Kyung Wee ◽

Seongsoo Lee

Keyword(s):

Low Voltage ◽

Offset Cancellation ◽

Sense Amplifier

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Cell Charge Loss by Formation of Inversion Channel in DRAM

ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2020p0277 ◽

2020 ◽

Author(s):

Hoonchang Yang ◽

Keunchul Ryu ◽

Dongin Seo ◽

Kyoungrak Cho ◽

Junsik Park ◽

...

Keyword(s):

Leakage Current ◽

Study Data ◽

Electron Loss ◽

Voltage Level ◽

Sense Amplifier ◽

Read Operation ◽

Related Cell ◽

Inversion Channel ◽

Charge Loss ◽

Cell Capacitance

Abstract As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].

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