Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories

With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.

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Study on Cross-Coupled-Based Sensing Circuits for Nonvolatile Flip-Flops Operating in Near/Subthreshold Voltage Region

Micromachines ◽

10.3390/mi12101177 ◽

2021 ◽

Vol 12 (10) ◽

pp. 1177

Author(s):

Taehui Na

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Test Chip ◽

Offset Voltage ◽

Higher Power ◽

Measurement Results ◽

Subthreshold Voltage ◽

The Cost ◽

Voltage Region

To date, most studies focus on complex designs to realize offset cancelation characteristics in nonvolatile flip-flops (NV-FFs). However, complex designs using switches are ineffective for offset cancelation in the near/subthreshold voltage region because switches become critical contributors to the offset voltage. To address this problem, this paper proposes a novel cross-coupled NMOS-based sensing circuit (CCN-SC) capable of improving the restore yield, based on the concept that the simplest is the best, of an NV-FF operating in the near/subthreshold voltage region. Measurement results using a 65 nm test chip demonstrate that with the proposed CCN-SC, the restore yield is increased by more than 25 times at a supply voltage of 0.35 V, compared to that with a cross-coupled inverter-based SC, at the cost of 18× higher power consumption.

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A SELECTIVE REPLACEMENT METHOD FOR TIMING-ERROR-PREDICTING FLIP-FLOPS

Journal of Circuits System and Computers ◽

10.1142/s0218126612400130 ◽

2012 ◽

Vol 21 (06) ◽

pp. 1240013 ◽

Cited By ~ 1

Author(s):

YUJI KUNITAKE ◽

TOSHINORI SATO ◽

HIROTO YASUURA ◽

TAKANORI HAYASHIDA

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Large Area ◽

Power Supply Voltage ◽

Timing Error ◽

Large Power ◽

Technology Scaling ◽

Replacement Method ◽

Area Overhead ◽

Spatial Redundancy

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. The design margin in the supply voltage will be overestimated, which results in large power consumption. To eliminate the waste power consumption due to the overestimated power supply voltage, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named Canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.

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A high-performance very low-voltage current sense amplifier for nonvolatile memories

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2004.840985 ◽

2005 ◽

Vol 40 (2) ◽

pp. 507-514 ◽

Cited By ~ 36

Author(s):

A. Conte ◽

G.L. Giudice ◽

G. Palumbo ◽

A. Signorello

Keyword(s):

High Performance ◽

Low Voltage ◽

Sense Amplifier ◽

Nonvolatile Memories

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A 93.4% Efficiency 8-mV Offset Voltage Constant On-Time Buck Converter With an Offset Cancellation Technique

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2019.2948208 ◽

2020 ◽

Vol 67 (10) ◽

pp. 2069-2073

Author(s):

Robert Chen-Hao Chang ◽

Wei-Chih Chen ◽

Jerry Kuei-Shou Huang

Keyword(s):

Buck Converter ◽

Offset Cancellation ◽

Offset Voltage

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A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

Journal of Circuits System and Computers ◽

10.1142/s0218126620501303 ◽

2019 ◽

Vol 29 (08) ◽

pp. 2050130 ◽

Cited By ~ 1

Author(s):

Jagdeep Kaur Sahani ◽

Anil Singh ◽

Alpana Agarwal

Keyword(s):

Phase Noise ◽

Supply Voltage ◽

Dead Zone ◽

Dynamic Logic ◽

Cmos Technology ◽

Control Voltage ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Cmos Inverter ◽

Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

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Low-Power CMOS Integrated Hall Switch Sensor

Active and Passive Electronic Components ◽

10.1155/2017/5375619 ◽

2017 ◽

Vol 2017 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Rongshan Wei ◽

Shizhong Guo ◽

Shanzhi Yang

Keyword(s):

Supply Voltage ◽

Reducing Power ◽

Cmos Technology ◽

Sleep Mode ◽

Test Results ◽

Offset Voltage ◽

Current Consumption ◽

Low Power Cmos ◽

Switch Circuit ◽

Hall Element

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.

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Ultra-Low-Voltage Inverter-Based Operational Transconductance Amplifiers with Voltage Gain Enhancement by Improved Composite Transistors

Electronics ◽

10.3390/electronics9091410 ◽

2020 ◽

Vol 9 (9) ◽

pp. 1410

Author(s):

Luis Henrique Rodovalho ◽

Orazio Aiello ◽

Cesar Ramos Rodrigues

Keyword(s):

Low Voltage ◽

Supply Voltage ◽

Voltage Gain ◽

Design Environment ◽

Operational Transconductance Amplifiers ◽

Gain Enhancement ◽

Transconductance Amplifiers ◽

Forward Body Bias ◽

The Cost ◽

The Impact

This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance figures is demonstrated through simulations of two OTAs. The first OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 μm2. The latter allies the forward-body-bias approach with the benefit of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 μm2. The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.

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Clustering approaches to improve the performance of low cost air pollution sensors

Faraday Discussions ◽

10.1039/c7fd00020k ◽

2017 ◽

Vol 200 ◽

pp. 621-637 ◽

Cited By ~ 16

Author(s):

Katie R. Smith ◽

Peter M. Edwards ◽

Mathew J. Evans ◽

James D. Lee ◽

Marvin D. Shaw ◽

...

Keyword(s):

Air Pollution ◽

Supply Voltage ◽

Low Cost ◽

Linear Interpolation ◽

External Reference ◽

Single Chemical ◽

Cost Competitiveness ◽

Sensor Signals ◽

Co Sensor ◽

The Cost

Low cost air pollution sensors have substantial potential for atmospheric research and for the applied control of pollution in the urban environment, including more localized warnings to the public. The current generation of single-chemical gas sensors experience degrees of interference from other co-pollutants and have sensitivity to environmental factors such as temperature, wind speed and supply voltage. There are uncertainties introduced also because of sensor-to-sensor response variability, although this is less well reported. The sensitivity of Metal Oxide Sensors (MOS) to volatile organic compounds (VOCs) changed with relative humidity (RH) by up to a factor of five over the range of 19–90% RH and with an uncertainty in the correction of a factor of two at any given RH. The short-term (second to minute) stabilities of MOS and electrochemical CO sensor responses were reasonable. During more extended use, inter-sensor quantitative comparability was degraded due to unpredictable variability in individual sensor responses (to either measurand or interference or both) drifting over timescales of several hours to days. For timescales longer than a week identical sensors showed slow, often downwards, drifts in their responses which diverged across six CO sensors by up to 30% after two weeks. The measurement derived from the median sensor within clusters of 6, 8 and up to 21 sensors was evaluated against individual sensor performance and external reference values. The clustered approach maintained the cost competitiveness of a sensor device, but the median concentration from the ensemble of sensor signals largely eliminated the randomised hour-to-day response drift seen in individual sensors and excluded the effects of small numbers of poorly performing sensors that drifted significantly over longer time periods. The results demonstrate that for individual sensors to be optimally comparable to one another, and to reference instruments, they would likely require frequent calibration. The use of a cluster median value eliminates unpredictable medium term response changes, and other longer term outlier behaviours, extending the likely period needed between calibration and making a linear interpolation between calibrations more appropriate. Through the use of sensor clusters rather than individual sensors, existing low cost technologies could deliver significantly improved quality of observations.

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