Multi-level approaches to low power 16-bit ALU design

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) ◽

10.1109/apasic.1999.824052 ◽

2003 ◽

Author(s):

Beom Seon Ryu ◽

Hyoung Sok Oh ◽

Kie Hak Shim ◽

Kie Young Lee ◽

Tae Won Cho

Keyword(s):

Low Power ◽

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A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

International Journal of Circuit Theory and Applications ◽

10.1002/cta.2938 ◽

2021 ◽

Author(s):

Hossein Firouzkouhi ◽

Mohammadreza Ashraf

Keyword(s):

Low Power ◽

Current Source ◽

Pipelined Adc ◽

Ultra Low Power ◽

Multi Level ◽

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Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture

Circuits Systems and Signal Processing ◽

10.1007/s00034-017-0553-2 ◽

2017 ◽

Vol 37 (1) ◽

pp. 444-458 ◽

Author(s):

Saad Al-Azawi

Keyword(s):

Wavelet Transform ◽

Low Power ◽

Discrete Wavelet Transform ◽

Discrete Wavelet ◽

Low Area ◽

Multi Level ◽

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Adaptive Circuit Approaches to Low-Power Multi-Level/Cell FeFET Memory

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/asp-dac47756.2020.9045106 ◽

2020 ◽

Author(s):

Juejian Wu ◽

Yixin Xu ◽

Bowen Xue ◽

Yu Wang ◽

Yongpan Liu ◽

...

Keyword(s):

Low Power ◽

Multi Level ◽

Adaptive Circuit

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Formation free low power resistive switching memory using IrOx/AlOx/W cross-point with excellent uniformity and multi level operation

10.7567/ssdm.2011.f-8-4 ◽

2011 ◽

Author(s):

W. Banerjee ◽

S. Z. Rahaman ◽

S. Maikap

Keyword(s):

Low Power ◽

Resistive Switching ◽

Cross Point ◽

Resistive Switching Memory ◽

Multi Level ◽

Switching Memory

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Multi-level low swing voltage values for low power design applications

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196) ◽

10.1109/iscas.2001.922306 ◽

2002 ◽

Author(s):

A. Rjoub ◽

M. Alrousan ◽

O. Jarrah ◽

O. Koufopavlou

Keyword(s):

Low Power ◽

Low Power Design ◽

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Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

2006 IEEE Workshop on Signal Processing Systems Design and Implementation ◽

10.1109/sips.2006.352599 ◽

2006 ◽

Author(s):

Wei Liu ◽

Junrye Rho ◽

Wonyong Sung

Keyword(s):

Low Power ◽

Error Correction ◽

High Throughput ◽

Vlsi Design ◽

Flash Memories ◽

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A multi-level DRAM with fast read and low power consumption

2005 IEEE Workshop on Microelectronics and Electron Devices, 2005. WMED '05. ◽

10.1109/wmed.2005.1431619 ◽

2005 ◽

Author(s):

Bo Liu ◽

J.F. Frenzel ◽

R.B. Wells

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

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Low Power State Assignment Targeting Two- And Multi-level Logic Implementations

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1994.629748 ◽

2005 ◽

Author(s):

Chi-Ymg Tsui ◽

M. Pedram ◽

Chih-Ang Chen ◽

A.M. Despain

Keyword(s):

Low Power ◽

State Assignment ◽

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Low-Power Multi-level Modulation of InP MZM with In-line Centipede Structure Directly Driven by CMOS IC

2013 18th OptoElectronics and Communications Conference held jointly with 2013 International Conference on Photonics in Switching ◽

10.1364/oecc_ps.2013.wk2_3 ◽

2013 ◽

Author(s):

Tomoyuki Yamase ◽

Mineto Sato ◽

Hidemi Noguchi ◽

Kenji Sato ◽

Tomoaki Kato

Keyword(s):

Low Power ◽

Multi Level ◽

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Skip-duty control method for minimizing switching stress in low-power multi-level Dc-Dc converters

2015 IEEE 16th Workshop on Control and Modeling for Power Electronics (COMPEL) ◽

10.1109/compel.2015.7236465 ◽

2015 ◽

Author(s):

Nenad Vukadinovic ◽

Aleksandar Prodic ◽

Brett A. Miwa ◽

Cory B. Arnold ◽

Michael W. Baker

Keyword(s):

Low Power ◽

Control Method ◽

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