An Investigation for Leakage Reduction of Dual Transmission Gate Adiabatic Logic Circuits with Power-Gating Schemes in Scaled CMOS Processes

2010 ◽  
Author(s):  
Li Su ◽  
Weiqiang Zhang ◽  
Lifang Ye ◽  
Xuhua Shi ◽  
Jianping Hu
Keyword(s):  
Logic Circuits ◽  
Power Gating ◽  
Leakage Reduction ◽  
Transmission Gate ◽  
Adiabatic Logic ◽  
Dual Transmission ◽  
Scaled Cmos ◽  
Cmos Processes

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 281-286 ◽  
Author(s):  
Jia Guo Zhu ◽  
Jian Ping Hu
Keyword(s):  
Single Phase ◽  
Sleep Mode ◽  
Power Gating ◽  
Register File ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
X 32 ◽  
Cmos Processes

With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.

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