Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

A New P-Type Clocked Adiabatic Logic for Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1930-1936 ◽  
Author(s):  
Jian Ping Hu ◽  
Li Fang Ye ◽  
Li Su
Keyword(s):  
Power Dissipation ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Total Power ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
P Type ◽  
Cmos Processes

Leakage current is becoming a significant contributor to power dissipations in nanometer CMOS circuits due to the scaling of oxide thickness. This paper proposes a new P-type clocked adiabatic logic (P-CAL) to reduce gate leakage based on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones in nanometer CMOS processes using gate oxide materials. Based on the power dissipation models of adiabatic circuits, the estimation technology for the active leakage dissipations of P-CAL circuits is proposed. The active leakage dissipations are estimated by testing total leakage dissipations with additional load capacitances using SPICE simulations. Compared to N-type clocked adiabatic logic (N-CAL) circuits, the total power and leakage power dissipation of P-type CAL circuits are reduced greatly.

P-Type ECRL Circuits for Gate-Leakage Reduction in Nanometer CMOS Processes with Gate Oxide Materials

2010 ◽  
Vol 29-32 ◽  
pp. 1919-1924 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Gate Oxide ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Power Supply Voltage ◽  
Flip Flop ◽  
Nanometer Cmos ◽  
P Type ◽  
Cmos Processes

With the decrease of the power supply voltage, the thickness of the gate oxide has been also scaled down in CMOS technologies using gate oxide materials. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. Base on the fact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, this paper propose a P-type efficient charge recovery logic (P-ECRL) to reduce leakage dissipations in nanometer CMOS processes with gate oxide materials. For an example, a J-K flip-flop and a mode-10 counter using four-phase P-ECRL circuits are verified. All circuits are simulated using 90nm and 45nm CMOS processes with gate oxide materials. The proposed P-ECRL circuits show significant improvement in terms of power consumption over the traditional N-type ECRL counterparts.

Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes

2010 ◽  
Vol 108-111 ◽  
pp. 625-630 ◽  
Author(s):  
Yang Bo Wu ◽  
Jian Ping Hu ◽  
Hong Li
Keyword(s):  
Significant Proportion ◽  
Power Estimation ◽  
Low Power Design ◽  
Leakage Power ◽  
Cmos Process ◽  
Cmos Circuits ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor

In deep sub-micro CMOS process, the leakage power is becoming a significant proportion in power dissipation. Hence, estimating the leakage power of CMOS circuits is very important in low-power design. In this paper, an estimation technology for the total leakage power of adiabatic logic circuits by using SPICE is proposed. The basic principle of power estimation for traditional CMOS circuits using SPICE is introduced. According to the energy dissipation characteristic of adiabatic circuits, the estimation technology for leakage power is discussed. Taken as an example, the estimation for total leakage power dissipations of PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits is illustrated using the proposed estimation technology.

P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits

2010 ◽  
Vol 159 ◽  
pp. 155-161
Author(s):  
Jin Tao Jiang ◽  
Yu Zhang ◽  
Jian Ping Hu
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Gate Structure ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
P Type ◽  
Cmos Processes

With rapid technology scaling, the proportion of the leakage power catches up with dynamic power gradually. The leakage dissipation through the gate oxide is becoming an important component of power consumption in currently used nanometer CMOS processes without metal gate structure. This paper presents adiabatic sequential circuits using P-type complementary pass-transistor adiabatic logic circuit (P-CPAL) to reduce the gate-leakage power dissipations. A practical sequential system with a mode-10 counter is demonstrated using the P-CPAL scheme. All circuits are simulated using HSPICE under 65nm and 90nm CMOS processes. Simulations show that the mode-10 counter using P-CPAL circuits obtains significant improvement in terms of power consumption over the traditional N-type CPAL counterparts.

Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

2010 ◽  
Vol 159 ◽  
pp. 180-185 ◽  
Author(s):  
Jian Ping Hu ◽  
Yu Zhang
Keyword(s):  
Energy Savings ◽  
Cmos Process ◽  
Gate Length ◽  
Mos Transistors ◽  
Traffic Light ◽  
Leakage Currents ◽  
Two Phase ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
The One

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

Complementary Pass-Transistor Adiabatic Logic Using Dual Threshold CMOS Techniques

2010 ◽  
Vol 39 ◽  
pp. 55-60 ◽  
Author(s):  
Bin Bin Lu ◽  
Jian Ping Hu
Keyword(s):  
Energy Dissipation ◽  
Full Adder ◽  
Logic Circuits ◽  
Cmos Circuits ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Simulation Results ◽  
Scaling Down

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 281-286 ◽  
Author(s):  
Jia Guo Zhu ◽  
Jian Ping Hu
Keyword(s):  
Single Phase ◽  
Sleep Mode ◽  
Power Gating ◽  
Register File ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Nanometer Cmos ◽  
Adiabatic Logic ◽  
X 32 ◽  
Cmos Processes

With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.

Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

2010 ◽  
Vol 121-122 ◽  
pp. 97-102 ◽  
Author(s):  
Wei Qiang Zhang ◽  
Li Su ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Power Dissipation ◽  
Low Power Design ◽  
Logic Circuits ◽  
Leakage Power ◽  
Nanometer Cmos ◽  
Wide Range ◽  
Adiabatic Logic ◽  
Total Leakage ◽  
Pass Transistor ◽  
Simulation Results

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

Sign in / Sign up

Export Citation Format

Share Document