Design methodology and applications of SiGe BiCMOS cascode opamps with up to 37-GHz unity gain bandwidth

2005 ◽  
Author(s):  
S.P. Voinigescu ◽  
R. Beerkens ◽  
T.O. Dickson ◽  
T. Chalvatzis
Keyword(s):  
Design Methodology ◽  
Gain Bandwidth ◽  
Sige Bicmos ◽  
Unity Gain

scholarly journals Design of a 0.13 µm SiGe Limiting Amplifier with 14.6 THz Gain-Bandwidth-Product

2017 ◽  
Vol 15 ◽  
pp. 115-121
Author(s):  
Sehoon Park ◽  
Xuan-Quang Du ◽  
Markus Grözing ◽  
Manfred Berroth
Keyword(s):  
Group Delay ◽  
Supply Voltage ◽  
Input Voltage ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Chip Area ◽  
Limiting Amplifier ◽  
Inductive Peaking ◽  
Bicmos Technology ◽  
Sige Bicmos

Abstract. This paper presents the design of a limiting amplifier with 1-to-3 fan-out implementation in a 0.13 µm SiGe BiCMOS technology and gives a detailed guideline to determine the circuit parameters of the amplifier for optimum high-frequency performance based on simplified gain estimations. The proposed design uses a Cherry-Hooper topology for bandwidth enhancement and is optimized for maximum group delay flatness to minimize phase distortion of the input signal. With regard to a high integration density and a small chip area, the design employs no passive inductors which might be used to boost the circuit bandwidth with inductive peaking. On a RLC-extracted post-layout simulation level, the limiting amplifier exhibits a gain-bandwidth-product of 14.6 THz with 56.6 dB voltage gain and 21.5 GHz 3 dB bandwidth at a peak-to-peak input voltage of 1.5 mV. The group delay variation within the 3 dB bandwidth is less than 0.5 ps and the power dissipation at a power supply voltage of 3 V including output drivers is 837 mW.

scholarly journals Design of a 2 GHz Linear-in-dB Variable-Gain Amplifier with 80-dB Gain Range

2014 ◽  
Vol 2014 ◽  
pp. 1-7
Author(s):  
Zhengyu Sun ◽  
Yuepeng Yan
Keyword(s):  
Current Gain ◽  
Variable Gain Amplifier ◽  
Current Steering ◽  
Gain Bandwidth ◽  
Broad Bandwidth ◽  
Variable Gain ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Bicmos Process ◽  
Steering Current

A broadband linear-in-dB variable-gain amplifier (VGA) circuit is implemented in 0.18 μm SiGe BiCMOS process. The VGA comprises two cascaded variable-gain core, in which a hybrid current-steering current gain cell is inserted in the Cherry-Hooper amplifier to maintain a broad bandwidth while covering a wide gain range. Postlayout simulation results confirm that the proposed circuit achieves a 2 GHz 3-dB bandwidth with wide linear-in-dB gain tuning range from −19 dB up to 61 dB. The amplifier offers a competitive gain bandwidth product of 2805 GHz at the maximum gain for a 110-GHz ftBiCMOS technology. The amplifier core consumes 31 mW from a 3.3 V supply and occupies active area of 280 μm by 140 μm.

A Fast Low Dropout Regulator with High Slew Rate and Large Unity-Gain Bandwidth

2013 ◽  
Vol 13 (4) ◽  
pp. 263-271 ◽  
Author(s):  
Younghun Ko ◽  
Yeongshin Jang ◽  
Sok-Kyun Han ◽  
Sang-Gug Lee
Keyword(s):  
Slew Rate ◽  
Gain Bandwidth ◽  
Unity Gain ◽  
Low Dropout Regulator

ACTIVE-FEEDBACK SINGLE MILLER CAPACITOR FREQUENCY COMPENSATION TECHNIQUES FOR THREE-STAGE AMPLIFIERS

2010 ◽  
Vol 19 (07) ◽  
pp. 1381-1398 ◽  
Author(s):  
MOHAMMAD YAVARI
Keyword(s):  
Low Power ◽  
Small Signal ◽  
Frequency Compensation ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Active Feedback ◽  
In Series ◽  
Unity Gain ◽  
Simulation Results ◽  
A Current

This paper presents two novel active-feedback single Miller capacitor frequency compensation techniques for low-power three-stage amplifiers. These techniques include the active-feedback single Miller capacitor frequency compensation (AFSMC) and the dual active-feedback single Miller capacitor frequency compensation (DAFSMC). In the proposed techniques, only one Miller capacitor in series with a current buffer is utilized. The main advantages of the proposed three-stage amplifiers are the enhanced unity-gain bandwidth and the reduced silicon area. Small-signal analyses are performed and the design equations are obtained. Extensive HSPICE simulation results are provided to show the usefulness of the proposed AFSMC and DAFSMC amplifiers in both large and small capacitive loads.

Analysis and design of a high-gain 100–180-GHz differential power amplifier in 130 nm SiGe BiCMOS

2017 ◽  
Vol 9 (6) ◽  
pp. 1231-1239
Author(s):  
Faisal Ahmed ◽  
Muhammad Furqan ◽  
Klaus Aufinger ◽  
Andreas Stelzer
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Gain ◽  
Small Signal ◽  
Gain Bandwidth ◽  
Band Frequency ◽  
Analysis And Design ◽  
Differential Gain ◽  
Bicmos Technology ◽  
Sige Bicmos

This paper presents the design and measurement results of a high-gain D-band broadband power amplifier (PA) implemented in a 130 nm SiGe BiCMOS technology. The topology of the PA is based on four differential cascode stages with interstage matching networks. A detailed analysis of the frequency behavior of the transimpedance-gain of the common-base stage of the cascode is presented by means of small-signal equivalent circuits, when the proposed four-reactance wideband matching network is used for output matching to the subsequent stage. The effect of the size of the active devices, in achieving a desired gain, bandwidth, and output power, is investigated. The fabricated D-band amplifier is characterized on-wafer demonstrating a peak differential gain and output power of about 25 dB and 11 dBm, respectively, while utilizing a DC power of 262 mW from a 2.7 V supply. The 3-dB small-signal bandwidth of the PA spans from 100 to 180 GHz (limited by the measurement setup), making it the first SiGe-based PA to cover the entire D-band frequency range. The PA achieves a state-of-the-art differential gain-bandwidth product of around 1.4 THz and the highest GBW/PDCratio of 5.2 GHz/mW among all D-Band Si-based PAs.

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