Current mobile phone applications demand high performance from the DSP, and future
generations are likely to require even greater throughput. However, it is important to
balance these processing demands against the requirement of low power consumption
for extended battery lifetime. A novel low-power digital signal processor (DSP)
architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses
these requirements through a multi-level power reduction strategy. A parallel architecture
and configurable compressed instruction set meets the throughput requirements
without excessive program memory bandwidth, while a large register file reduces the
cost of data accesses. Sign-magnitude representation is used for data, to reduce switching
activity within the datapath. Asynchronous design gives fine-grained activity control
without the complexities of clock gating, and gives low electromagnetic interference.
Finally, the operational model of the target application allows for a reduced interrupt
structure, simplifying processor design by avoiding the need for exact exceptions.