A critical-path monitor for DVFS systems without datapath replication

Author(s):  
Hernan Aparicio ◽  
Pablo Ituero ◽  
Marisa Lopez-Vallejo
Keyword(s):  
2019 ◽  
Vol 7 (1) ◽  
pp. 256-259
Author(s):  
P.Balasowandari ◽  
Dr. V.Anusuya

Author(s):  
Totska Olesia ◽  
Glovatsky Anastasia

The purpose of the article is to plan a project of an electric vehicle technicalassistance point. the methodology of the study is to use the critical path method.the scientific novelty of the obtained results is that the article describes the practicalaspects of project planning of the creation of an electric vehicle technical assistancepoint. In particular, the tasks of the project are described, labor, material and financialresources necessary for its realization are specified. conclusions. The implementationof the developed project will effectively manage the content, time and resources ofthe project of the creation of an electric vehicle technical assistance point.


Author(s):  
R. Irawan

Leap frog concept was created to address the loss of single joint rig agility and drive the cycle time average lower than ever. The idea is to move the preparation step into a background activity that includes moving the equipment, killing the well, dismantling the wellhead and installing the well control equipment/BOP before the rig came in. To realize the idea, a second set of equipment is provided along with the manpower. By moving the preparation step, the goal is to eliminate a 50% portion of the job from the critical path. The practice is currently performed in tubing pump wells on land operations. However, the work concept could be implemented for other type of wells, especially ESP wells. After implementation, the cycle time average went down from 18 hours to 11 hours per job, or down by ~40%. The toolpusher also reports more focused operations due to reduced scope and less crew to work with, making the leap frog operation safer and more reliable. Splitting the routine services into 2 parts not only shortened the process but it also reduces noise that usually appear in the preparation process. The team are rarely seen waiting on moving support problems that were usually seen in the conventional process. Having the new process implemented, the team had successfully not only lowered cycle time, but also eliminated several problems in one step. Other benefits from leap frog implementation is adding rig count virtually to the actual physical rig available on location, and also adding rig capacity and completing more jobs compared to the conventional rig. In other parts, leap frog faced some limitation and challenges, such as: limited equipment capability for leap frog remote team to work on stuck plunger, thus hindering its leap frog capability, and working in un-restricted/un-clustered area which disturb the moving process and operation safety.


2006 ◽  
Vol 14 (7S_Part_20) ◽  
pp. P1076-P1076
Author(s):  
Daniela J. Conrado ◽  
Timothy Nicholas ◽  
Jackson Burton ◽  
Stephen P. Arnerić ◽  
Danny Chen ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 231
Author(s):  
Chester Sungchung Park ◽  
Sunwoo Kim ◽  
Jooho Wang ◽  
Sungkyung Park

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).


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