Impact of calibrated band-tails on the subthreshold swing of pocketed TFETs

Author(s):  
Jasper Bizindavyi ◽  
Anne S. Verhulst ◽  
Bart Soree ◽  
Guido Groeseneken
2017 ◽  
Vol 38 (12) ◽  
pp. 1661-1664 ◽  
Author(s):  
E. Memisevic ◽  
E. Lind ◽  
M. Hellenbrand ◽  
J. Svensson ◽  
L.-E. Wernersson

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 


2021 ◽  
Vol 129 (4) ◽  
pp. 045701
Author(s):  
Arnout Beckers ◽  
Dominique Beckers ◽  
Farzan Jazaeri ◽  
Bertrand Parvais ◽  
Christian Enz
Keyword(s):  

2021 ◽  
Author(s):  
Yongbiao Zhai ◽  
Zihao Feng ◽  
Ye Zhou ◽  
Su-Ting Han

We review the physics, design, and optimization of four steep-slope transistors and demonstrate their potential and drawbacks.


2012 ◽  
Vol 717-720 ◽  
pp. 1059-1064 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Lin Cheng ◽  
Sarit Dhar ◽  
Craig Capell ◽  
Charlotte Jonas ◽  
...  

We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.


2020 ◽  
Vol 51 (1) ◽  
pp. 1358-1361
Author(s):  
Takao Saito ◽  
Yosuke Kanzaki ◽  
Masahiko Miwa ◽  
Masaki Yamanaka ◽  
Yi Sun ◽  
...  

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