A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

2017 ◽  
Vol 5 (16) ◽  
pp. 3932-3936 ◽  
Author(s):  
Wenhui Lu ◽  
Shuai Zhang ◽  
Enqi Dai ◽  
Bin Miao ◽  
Yiran Peng ◽  
...  

Si/PEDOT:PSS core/shell nanowire hetero-junctions with adjustable electrical characteristics are reported. They exhibit an ohmic behavior ascribed to p-type Si/PEDOT:PSS, whereas n-type Si/PEDOT:PSS displays a rectifying nature.


2013 ◽  
Vol 747 ◽  
pp. 526-529
Author(s):  
Bo Yuan Su ◽  
Meng Chun Chen ◽  
Sheng Yuan Chu ◽  
Yang Der Juang

In this paper, the carbon nanotube was well dispersed into the poly (3,4-ethylenedioxythiophene) poly (styrenesulfonate) (PEDOTPSS) solution with a best concentration of 4 mg/ml. The prepared sol was spun on poly (ether sulfone) (PES) substrates, showing sheet resistance as low as 19.8 Ω/sq and the high average transmittance over 90 %. The change in optical and electrical properties due to poly (ether sulfone) (PES) substrate was investigated to understand the failure mechanisms. For realizing the bending effect on electrical performance, the pre-deposited ZnO buffer was introduced to improve the deterioration during the repeated bending test. The composite polymer enhanced the electrical conductivity with less detrimental effect on the optical transparency, which suggests the potential transparent conductive films for use in developing optical and electrical device.


1994 ◽  
Vol 336 ◽  
Author(s):  
I. D. French ◽  
C. J. Curling ◽  
A.L. Goodyear

ABSTRACTMulti-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easy to produce individual layers optimised for electrical performance that will physically “pull off’ underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.


2017 ◽  
Vol 2017 ◽  
pp. 1-6 ◽  
Author(s):  
Guru P. Neupane ◽  
Minh Dao Tran ◽  
Hyun Kim ◽  
Jeongyong Kim

Monolayer MoS2 (1L-MoS2) is an ideal platform to examine and manipulate two dimensionally confined exciton complexes, which provides a large variety of modulating the optical and electrical properties of 1L-MoS2. Extensive studies of external doping and hybridization exhibit the possibilities of engineering the optical and electrical performance of 1L-MoS2. However, biomodifications of 1L-MoS2 and the characterization and applications of such hybrid structures are rarely reported. In this paper, we present a bio-MoS2 hybrid structure fabricated by laterally stretching strands of DNAs on CVD-grown 1L-MoS2. We observed a strong modification of photoluminescence and Raman spectra with reduced PL intensity and red-shift of PL peak and Raman peaks, which were attributed to electron doping by the DNAs and the presence of tensile strain in 1L-MoS2. Moreover, we observed a significant enhancement of electric mobility in the DNA/1L-MoS2 hybrid compared to that in the pristine 1L-MoS2, which may have been caused by the induced strain in 1L-MoS2.


1994 ◽  
Vol 345 ◽  
Author(s):  
I. D. French ◽  
C. J. Curling ◽  
A. L. Goodyear

AbstractMulti-layer devices based on thin films in Large Area Electronics have different intrinsic and extrinsic properties that must be optimised to produce the correct physical shape of the device, in addition to having acceptable electrical characteristics. For instance it is quite easyto produce individual layers optimised for electrical performance that will physically “pull off” underlying films, or result in poor step coverage. The factors that must be considered include mechanical stress, etching rates and profiles, thickness and stoichiometry uniformity, and thermal budgets, as well as electrical characteristics. This paper gives an example of silicon nitride optimisation for use in a-Si:H TFT projection displays. Three different silicon nitride layers were included to give a storage capacitor, together with controlled etch profiles for step coverage. The layers were optimised with respect to several different parameters in the minimum number of depositions by the use of experimental design techniques.


2003 ◽  
Vol 796 ◽  
Author(s):  
D. Hong ◽  
N. L. Dehuff ◽  
R. E. Presley ◽  
C. L. Munsee ◽  
J. P. Bender ◽  
...  

ABSTRACTTransparent electronics is an embryonic technology whose objective is the realization of invisible electronic circuits. We have recently reported the fabrication of a novel n-channel transparent thin-film transistor (TTFT). [1] This ZnO-based TTFT is highly transparent and exhibits electrical characteristics that appear to be suitable for implementation as a transparent select-transistor in each pixel of an active-matrix liquid-crystal display. Moreover, the processing technology used to fabricate this device is relatively simple and appears to be compatible with inexpensive glass substrate technology. The objective of the work reported herein is to summarize some of our recent TTFT electrical performance results. Materials, processing, and device structure details related to these devices appear in future publications.


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