Genetic algorithm for electro-mechanical co-optimization of a MEMS accelerometer comprising a mechanical motion pre-amplifier with a 2nd-order sigma delta modulator

Author(s):  
Chen Wang ◽  
Huafeng Liu ◽  
Yuan Wang ◽  
Xiaoxiao Song ◽  
Jian Bai ◽  
...  
2020 ◽  
Vol 6 (1) ◽  
Author(s):  
Chen Wang ◽  
Xiaoxiao Song ◽  
Weidong Fang ◽  
Fang Chen ◽  
Ioannis Zeimpekis ◽  
...  

AbstractThis paper describes a novel, semiautomated design methodology based on a genetic algorithm (GA) using freeform geometries for microelectromechanical systems (MEMS) devices. The proposed method can design MEMS devices comprising freeform geometries and optimize such MEMS devices to provide high sensitivity, large bandwidth, and large fabrication tolerances. The proposed method does not require much computation time or memory. The use of freeform geometries allows more degrees of freedom in the design process, improving the diversity and performance of MEMS devices. A MEMS accelerometer comprising a mechanical motion amplifier is presented to demonstrate the effectiveness of the design approach. Experimental results show an improvement in the product of sensitivity and bandwidth by 100% and a sensitivity improvement by 141% compared to the case of a device designed with conventional orthogonal shapes. Furthermore, excellent immunities to fabrication tolerance and parameter mismatch are achieved.


Sensors ◽  
2011 ◽  
Vol 11 (10) ◽  
pp. 9217-9232 ◽  
Author(s):  
Reuben Wilcock ◽  
Michael Kraft

2020 ◽  
Vol 34 (27) ◽  
pp. 2050302
Author(s):  
Dongliang Chen ◽  
Liang Yin ◽  
Qiang Fu ◽  
Yufeng Zhang ◽  
Xiaowei Liu

This paper proposes a novel digital readout interface for capacitive MEMS accelerometer. The digitalization is fulfilled by incorporating a 1-bit [Formula: see text] (sigma-delta) modulator into the closed servo loop. It both realizes a direct digital output efficiently and linearizes the electrostatic feedback force. To maintain the stability and improve loop linearity, a discrete-time proportional integral and differential (PID) compensator is used. It improves the in-band gain, enhances quantization noise suppressing ability and maintain the high-frequency phase margin at the same time. Thus the linearity and noise performance are improved. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology. Test results show that, the linearity is better than 0.1% and the noise floor is as low as 1 [Formula: see text]g/[Formula: see text].


2009 ◽  
Vol E92-C (6) ◽  
pp. 860-863 ◽  
Author(s):  
Lukas FUJCIK ◽  
Linus MICHAELI ◽  
Jiri HAZE ◽  
Radimir VRBA

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