Memristor based adaptive impedance and frequency tuning network

Author(s):  
Chithra Liz Palson ◽  
Deepti Das Krishna ◽  
Jimson Mathew ◽  
Babita Roslind Jose ◽  
Marco Ottavi ◽  
...  
Keyword(s):  
2008 ◽  
Vol 128 (7) ◽  
pp. 1015-1022
Author(s):  
Sheng Ge ◽  
Makoto Ichikawa ◽  
Atsushi Osa ◽  
Keiji Iramina ◽  
Hidetoshi Miike

2016 ◽  
Vol 75 (10) ◽  
pp. 887-894 ◽  
Author(s):  
R. I. Bilous ◽  
A. P. Motornenko ◽  
I. G. Skuratovskiy ◽  
O. I. Khazov

2012 ◽  
Vol 39 (11) ◽  
pp. 1082-1088
Author(s):  
Yin-Ting PENG ◽  
Qing PU ◽  
Xin-De SUN ◽  
Ji-Ping ZHANG

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.


Author(s):  
Titus Oyedokun ◽  
Riana H. Geschke ◽  
Tinus Stander

Abstract We present a tunable planar groove gap waveguide (PGGWG) resonant cavity at Ka-band. The cavity demonstrates varactor loading and biasing without bridging wires or annular rings, as commonly is required in conventional substrate-integrated waveguide (SIW) resonant cavities. A detailed co-simulation strategy is also presented, with indicative parametric tuning data. Measured results indicate a 4.48% continuous frequency tuning range of 32.52–33.98 GHz and a Qu tuning range of 63–85, corresponding to the DC bias voltages of 0–16 V. Discrepancies between simulated and measured results are analyzed, and traced to process variation in the multi-layer printed circuit board stack, as well as unaccounted varactor parasitics and surface roughness.


2021 ◽  
pp. 2000417
Author(s):  
Luigi Consolino ◽  
Annamaria Campa ◽  
Michele De Regis ◽  
Francesco Cappelli ◽  
Giacomo Scalari ◽  
...  

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