Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770449 ◽

2018 ◽

Author(s):

Chandan K. Pandey ◽

Saurabh Chaudhury

Keyword(s):

Double Gate ◽

Tunnel Fets ◽

Ambipolar Conduction

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Performance Analysis of Dual Metal Double Gate Tunnel-FETs for Ultralow Power Applications

Nanoelectronic Materials and Devices - Lecture Notes in Electrical Engineering ◽

10.1007/978-981-10-7191-1_2 ◽

2017 ◽

pp. 11-18 ◽

Author(s):

D. Gracia ◽

D. Nirmal

Keyword(s):

Performance Analysis ◽

Double Gate ◽

Ultralow Power ◽

Tunnel Fets ◽

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Performance enhancement of double-gate tunnel FETs using dual-metal and graded-channel configuration

International Journal of Nanoparticles ◽

10.1504/ijnp.2020.10027809 ◽

2020 ◽

Vol 12 (1/2) ◽

pp. 174

Author(s):

Saurabh Chaudhury ◽

Chandan Kumar Pandey

Keyword(s):

Performance Enhancement ◽

Double Gate ◽

Tunnel Fets ◽

Channel Configuration

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Performance enhancement of double-gate tunnel FETs using dual-metal and graded-channel configuration

International Journal of Nanoparticles ◽

10.1504/ijnp.2020.106007 ◽

2020 ◽

Vol 12 (1/2) ◽

pp. 174

Author(s):

Chandan Kumar Pandey ◽

Saurabh Chaudhury

Keyword(s):

Performance Enhancement ◽

Double Gate ◽

Tunnel Fets ◽

Channel Configuration

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Two-dimensional model of Dual Metal double gate tunnel FETs

2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE) ◽

10.1109/wiecon-ece.2015.7444001 ◽

2015 ◽

Author(s):

Samantha Lubaba Noor ◽

Samia Safa ◽

Md. Ziaur Rahman Khan

Keyword(s):

Double Gate ◽

Two Dimensional ◽

Dimensional Model ◽

Two Dimensional Model ◽

Tunnel Fets ◽

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Steep subthreshold swing analysis of dual metal drain dopingless double gate tunnel FETs based on ge-source with high-k for low power applications

2017 International Conference on Computing, Communication and Automation (ICCCA) ◽

10.1109/ccaa.2017.8230025 ◽

2017 ◽

Author(s):

Neeraj Sharma ◽

Sudakar Singh Chauhan

Keyword(s):

Low Power ◽

Subthreshold Swing ◽

Double Gate ◽

High K ◽

Tunnel Fets ◽

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Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs

IEEE Transactions on Electron Devices ◽

10.1109/ted.2016.2541181 ◽

2016 ◽

Vol 63 (5) ◽

pp. 2190-2196 ◽

Author(s):

Vishwa Prabhat ◽

Aloke K. Dutta

Keyword(s):

Surface Potential ◽

Drain Current ◽

Double Gate ◽

Tunnel Fets ◽

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Influence of Localized Interface Charges on Drain Current of Dual-Material Double-Gate Tunnel FETs

2018 3rd International Conference for Convergence in Technology (I2CT) ◽

10.1109/i2ct.2018.8529418 ◽

2018 ◽

Author(s):

Sanjay Kumar ◽

Kamlaksha Baral ◽

Sweta Chander ◽

P. K. Singh ◽

Kunal Singh ◽

...

Keyword(s):

Drain Current ◽

Double Gate ◽

Interface Charges ◽

Tunnel Fets ◽

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Performance of asymmetric gate oxide on gate-drain overlap in Si and Si1−xGex double gate tunnel FETs

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA) ◽

10.1109/vlsi-sata.2016.7593036 ◽

2016 ◽

Author(s):

S. Poorvasha ◽

B. Lakshmi

Keyword(s):

Double Gate ◽

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Double-gate Ge, In As-based tunnel FETs with enhanced ON-current

2016 International Conference on Communication and Signal Processing (ICCSP) ◽

10.1109/iccsp.2016.7754219 ◽

2016 ◽

Author(s):

Chebrolu Gopi ◽

Sudakar Singh Chauhan

Keyword(s):

Double Gate ◽

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Drive Current Boosting Using Pocket Implant Near to the Strained SiGe/Si Source with Single-Metal/Dual-Metal Double-Gate Tunnel Field-Effect Transistor

Proceeding of International Conference on Intelligent Communication, Control and Devices - Advances in Intelligent Systems and Computing ◽

10.1007/978-981-10-1708-7_110 ◽

2016 ◽

pp. 943-950

Author(s):

Prateek Jain ◽

Deepak Kumar

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Double Gate ◽

Drive Current ◽

Effect Transistor ◽

Tunnel Field Effect Transistor ◽

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