Process integrated of high aspect ratio copper dual damascene process

2009 ◽  
Author(s):  
Chun-Jen Weng
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
Dual Damascene ◽  
Damascene Process

Fabrication of Dual-Damascene Structures in Low Dielectric Constant Polymers for Multilevel Interconnects

1996 ◽  
Vol 427 ◽  
Author(s):  
R. Tacito ◽  
C. Steinbrüchel
Keyword(s):  
Dielectric Constant ◽  
Aspect Ratio ◽  
Silicon Dioxide ◽  
High Aspect Ratio ◽  
Reactive Ion Etching ◽  
Low Dielectric Constant ◽  
Ion Etching ◽  
Fine Line ◽  
Dual Damascene ◽  
Low Dielectric

AbstractParylene-n (pa-n) and benzocyclobutene (BCB) are novel candidate materials for interlevel dielectrics in future multilevel interconnects, due to their dielectric constant being much lower than that of silicon dioxide. We describe the fine line patterning of these materials by reactive ion etching in O2/CF4 plasmas. Examples of high aspect ratio trenches and dual damascene structures are presented involving processes with single and double hardmasks.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

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