Dual Damascene Process for FatWires in Copper/FSG Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

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Process window study of the stacked via structure in dual-damascene process

1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat. No.97CH36023) ◽

10.1109/issm.1997.664603 ◽

2002 ◽

Author(s):

T. Saitoh ◽

H. Wada ◽

K. Kitamura

Keyword(s):

Process Window ◽

Dual Damascene ◽

Damascene Process

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Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

Journal of The Electrochemical Society ◽

10.1149/1.1528944 ◽

2003 ◽

Vol 150 (1) ◽

pp. G58 ◽

Cited By ~ 4

Author(s):

Sang-Yun Lee ◽

Yong-Bae Kim ◽

Jeong Soo Byun

Keyword(s):

Antireflection Coating ◽

Dual Damascene ◽

Damascene Process ◽

193 Nm

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Aluminum Reflow Sputtering

MRS Bulletin ◽

10.1557/s0883769400045577 ◽

1995 ◽

Vol 20 (11) ◽

pp. 53-56 ◽

Cited By ~ 3

Author(s):

Kuniko Kikuta

Keyword(s):

Integrated Circuit ◽

High Speed ◽

Lower Cost ◽

High Reliability ◽

Device Fabrication ◽

Damascene Process ◽

Aspect Ratios ◽

Multi Level ◽

Poor Adhesion ◽

Lower Resistivity

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.

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