Enhancing The Accuracy of GPS Point Positioning by Modeling the Ionospheric Propagation Delay

Author(s):  
Abubakr Albashir ◽  
Kamal Abdellatif Sami ◽  
Mohammed Ahmedeltigani
MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 49-54 ◽  
Author(s):  
E. Todd Ryan ◽  
Andrew J. McKerrow ◽  
Jihperng Leu ◽  
Paul S. Ho

Continuing improvement in device density and performance has significantly affected the dimensions and complexity of the wiring structure for on-chip interconnects. These enhancements have led to a reduction in the wiring pitch and an increase in the number of wiring levels to fulfill demands for density and performance improvements. As device dimensions shrink to less than 0.25 μm, the propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant. Accordingly the interconnect delay now constitutes a major fraction of the total delay limiting the overall chip performance. Equally important is the processing complexity due to an increase in the number of wiring levels. This inevitably drives cost up by lowering the manufacturing yield due to an increase in defects and processing complexity.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILDs) and alternative architectures have surfaced to replace the current Al(Cu)/SiO2 interconnect technology. These alternative architectures will require the introduction of low-dielectric-constant k materials as the interlayer dielectrics and/or low-resistivity conductors such as copper. The electrical and thermomechanical properties of SiO2 are ideal for ILD applications, and a change to material with different properties has important process-integration implications. To facilitate the choice of an alternative ILD, it is necessary to establish general criterion for evaluating thin-film properties of candidate low-k materials, which can be later correlated with process-integration problems.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.


Author(s):  
Teresa V.V ◽  
Anand. B

Objective: In this research work presents an efficient way Carry Select Adder (CSLA) performance and estimation. The CSLA is utilized in several system to mitigate the issue of carry propagation delay that is happens by severally generating various carries and to get the sum, select a carry because of the uses of various pairs of RCA to provide the sum of the partial section also carry by consisting carry input but the CSLA isn't time economical, then by the multiplexers extreme total and carry is chosen in the selected section. Methodology: The fundamental plan of this work is to attain maximum speed and minimum power consumption by using Binary to Excess-1. Convertor rather than RCA within the regular CSLA. Here RCA denotes the Ripple Carry Adder section. At the span to more cut back the facility consumption, a method of CSLA with D LATCH is implemented during this research work. The look of Updated Efficient Area -Carry Select Adder (UEA-CSLA) is evaluated and intended in XILINX ISE design suite 14. 5 tools. This VLSI arrangement is utilized in picture preparing application by concluding the cerebrum tumor discovery. Conclusion: In this study, medicinal pictures estimation, investigation districts in the multi phantom picture isn't that much proficient to defeat this disadvantage here utilized hyper spectral picture method is presented a sifting procedure in VLSI innovation restriction of cerebrum tumor is performed Updated Efficient Area - Carry Select Adder propagation result dependent on Matrix Laboratory in the adaptation of R2018b.


2016 ◽  
Vol 914 (8) ◽  
pp. 26-30 ◽  
Author(s):  
A.V. Voytenko ◽  
◽  
V.L. Bykov ◽  

Entropy ◽  
2021 ◽  
Vol 23 (6) ◽  
pp. 676
Author(s):  
Dimitrios Z. Politis ◽  
Stelios M. Potirakis ◽  
Yiannis F. Contoyiannis ◽  
Sagardweep Biswas ◽  
Sudipta Sasmal ◽  
...  

In this work we present the statistical and criticality analysis of the very low frequency (VLF) sub-ionospheric propagation data recorded by a VLF/LF radio receiver which has recently been established at the University of West Attica in Athens (Greece). We investigate a very recent, strong (M6.9), and shallow earthquake (EQ) that occurred on 30 October 2020, very close to the northern coast of the island of Samos (Greece). We focus on the reception data from two VLF transmitters, located in Turkey and Israel, on the basis that the EQ’s epicenter was located within or very close to the 5th Fresnel zone, respectively, of the corresponding sub-ionospheric propagation path. Firstly, we employed in our study the conventional analyses known as the nighttime fluctuation method (NFM) and the terminator time method (TTM), aiming to reveal any statistical anomalies prior to the EQ’s occurrence. These analyses revealed statistical anomalies in the studied sub-ionospheric propagation paths within ~2 weeks and a few days before the EQ’s occurrence. Secondly, we performed criticality analysis using two well-established complex systems’ time series analysis methods—the natural time (NT) analysis method, and the method of critical fluctuations (MCF). The NT analysis method was applied to the VLF propagation quantities of the NFM, revealing criticality indications over a period of ~2 weeks prior to the Samos EQ, whereas MCF was applied to the raw receiver amplitude data, uncovering the time excerpts of the analyzed time series that present criticality which were closest before the Samos EQ. Interestingly, power-law indications were also found shortly after the EQ’s occurrence. However, it is shown that these do not correspond to criticality related to EQ preparation processes. Finally, it is noted that no other complex space-sourced or geophysical phenomenon that could disturb the lower ionosphere did occur during the studied time period or close after, corroborating the view that our results prior to the Samos EQ are likely related to this mainshock.


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