Design and implementation of binary and quaternary low power selective circuit using single electron transistor

In engineering and science, high operating speed, low power consumption, and high integration density equipment are financially indispensable. Single electron device (SED) is one such equipment. SEDs are capable of controlling the transport of only one electron through the tunneling transistor. It is single electron that is sufficient to store information in SED. Power consumed in the single electron circuit is very low in comparison with CMOS circuits. The processing speed of single electron transistor (SET) based device will be nearly close to electronic speed. SET attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences for the case of a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. For implementing a single electron transistor based voltmeter circuit, SET would be the best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling SEDs. A D Flip-Flop is implemented and based on this, two kinds of registers like sequence register and сode register are made.

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A PSPICE Fast Model for the Single Electron Transistor

International Journal of Wireless and Ad Hoc Communication ◽

10.54216/ijwac.000101 ◽

2019 ◽

pp. 08-23

Author(s):

Lobna Osman ◽

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

Electron Tunneling ◽

Electronic Devices ◽

Single Electron ◽

Single Electron Transistor ◽

Electrical Characteristics ◽

Nanoelectronic Devices ◽

Low Power Dissipation

Motivated by the merits of low power dissipation, ultra-small size, and high speed of many nanoelectronic devices, They have been demonstrated to ensure future progress. Single-electron devices became one of the most important nanoelectronic devices due to their interesting electrical characteristics and behavior. Many research efforts moved to describe their electrical characteristics to use them with conventional electronic devices. This paper deals with modeling and simulation of such new electronic devices. This paper presents a model for the Single Electron Transistor (SET) and its application in simulating hybrid SET/MOS ADC and DAC converters. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor. The proposed model is more flexible that is valid for a large range of drain to source voltage, valid for single or multi-gate SET and symmetric or asymmetric SET. Finally, using this model with MOSFET transistors to realize multi-bit Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC). The hybrid n-bit DAC nano-circuits are simulated for (n=4 and 8) using Orcad Capture PSPICE. The performance of the SET/MOS hybrid n-bit ADC circuits were simulated (for n=3 and 8). The results show that the transient operation of hybrid SET/MOS circuit-based DAC could successfully operate at 1000K while ADC could operate at 144K. This performance can be compared with the pure SET circuits, the proposed converter circuits have been enhanced in the drive capability and the power dissipation. Compared with the other SET/MOS hybrid circuit, the implemented converter circuits have low simulation time, high speed, high load drivability, and low power dissipation.

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