Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits

2019 ◽  
Author(s):  
A. Parveen ◽  
T. Tamil Selvi
Keyword(s):  
Low Power ◽  
Vlsi Circuits ◽  
Efficient Design ◽  
Power Efficient ◽  
Adiabatic Approach

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

scholarly journals Power Efficient Bit Lines: A Succinct Study

2021 ◽  
Vol 1714 (1) ◽  
pp. 012042
Author(s):  
J. Bhaskara Veeraveni ◽  
K. Devi Bhawani
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Vlsi Circuits ◽  
Power Circuit ◽  
Power Efficient ◽  
Lower Power ◽  
Consumption Reduction ◽  
Voltage Swing

Abstract Reducing the consumption of power in VLSI circuits is challenging. A low power circuit in multi-port memories for power consumption reduction in bit lines is presented here. In this circuit the power of wide gates used in memory bit lines is decreased by reducing the voltage swing of the pull-down network. Wide gates were simulated and the results showed 40% lower power consumption. Processors are another component where power dissipation is high. Various methods are used to decrease the power dissipation. A number of methods reduce bus transitions to limit the power dissipation.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

scholarly journals Performance analysis of coded 8-pssk system with MRC diversity in fading channels

2018 ◽  
Vol 7 (3.3) ◽  
pp. 107
Author(s):  
Jae Young Chun ◽  
Kee Soo Yeom ◽  
Eon. Gon. Kim
Keyword(s):  
Low Power ◽  
Fading Channels ◽  
Channel Coding ◽  
Performance Gain ◽  
Coding Gain ◽  
Power Efficient ◽  
Coding Scheme ◽  
Communication Technique ◽  
Increasing Demand ◽  
Diversity Technique

Due to the increasing demand for low power communication in the field of remote control & monitoring, it is necessary to introduce a communication technique to meet the various QoS requirements even in an inferior radio channels. In order to ensure these QoS requirements, we propose a communication technique that applies the channel code, diversity scheme into power-efficient modulation. It makes the radio possible to dramatically improve BER by reducing the uncertainty due to fading channels. A core of proposed communication technique is to maximize the performance gain by adopting diversity technique and channel coding scheme. Diversity gain and channel coding gain further increase the performance difference (gain) between power-efficient modulation and conventional modulation, resulting in a signification BER improvement. By adapting the proposed communication technique it is expected to improve the usability of low-power radio according to the satisfaction of the various QoS requirements.  

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