scholarly journals Power Efficient Bit Lines: A Succinct Study

2021 ◽  
Vol 1714 (1) ◽  
pp. 012042
Author(s):  
J. Bhaskara Veeraveni ◽  
K. Devi Bhawani
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Vlsi Circuits ◽  
Power Circuit ◽  
Power Efficient ◽  
Lower Power ◽  
Consumption Reduction ◽  
Voltage Swing

Abstract Reducing the consumption of power in VLSI circuits is challenging. A low power circuit in multi-port memories for power consumption reduction in bit lines is presented here. In this circuit the power of wide gates used in memory bit lines is decreased by reducing the voltage swing of the pull-down network. Wide gates were simulated and the results showed 40% lower power consumption. Processors are another component where power dissipation is high. Various methods are used to decrease the power dissipation. A number of methods reduce bus transitions to limit the power dissipation.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

2020 ◽  
Vol 10 (4) ◽  
pp. 457-470 ◽  
Author(s):  
Dipanjan Sen ◽  
Savio J. Sengupta ◽  
Swarnil Roy ◽  
Manash Chanda ◽  
Subir K. Sarkar
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Dominant Factor ◽  
Double Gate ◽  
Cmos Inverter ◽  
Ultra Low Power ◽  
Voltage Swing

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub & Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

scholarly journals Design and Analysis of Gate All Around Tunnel FET based Ring Oscillator Circuit

2019 ◽  
Vol 8 (2) ◽  
pp. 2415-2420
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Propagation Delay ◽  
Active Power ◽  
Vlsi Circuits ◽  
Ring Oscillator ◽  
Oscillator Circuit ◽  
Lower Power ◽  
Tunnel Fet ◽  
Simulation Results

In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillator. However, 0.43 ns and 0.17 ns of propagation delay is observed for GAATFET based ring oscillator and CMOS based ring oscillator circuit respectively. The obtained output waveform frequency for CMOS based ring oscillator is 2.5 times higher than the GAAATFET based ring oscillator. Further, undershoot is also investigated and it is found that the amplitude of undershoot in case of GAATFET based oscillator is roughly 6.5 times more as compared to CMOS based counterpart. The undershoot and delay observed in case of GAATFET based ring oscillator can be over-shaded by the fact that it has lower active power consumption than the CMOS based ring oscillator. Simulation results signify that GAATFET based ring oscillator can be deployed in future low power VLSI circuits and systems.

Analytical Study Of Full Adder Circuit Using Modified Glitch Free Cascadable Adiabatic Logic

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Neha Raghav ◽  
◽  
Malti Bansal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Analytical Study ◽  
Supply Voltage ◽  
Full Adder ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Adiabatic Logic

Nowadays, power dissipation is among the most dominant concerns in designing a VLSI circuits. Endless improvement in technology has points to an increased requirement for devices which have the basic characteristic of low power consumption. Hence power has turn into a demanding design parameter in low power and high-performance applications. The Adiabatic logic technique is becoming a solution to the dilemma of power dissipation. Adders with huge power consumption affect the overall efficiency of the system. Hence, in this paper, the proposed application of full adder circuit is shown using the Modified Glitch Free Cascadable Adiabatic Logic. The circuit is compared with the conventional CMOS Logic and the power dissipation analysis is simulated with supply voltage = 0.9 V, 1.2 V and 1.8 V to analyze the pattern followed with supply variation at different temperature range. Similarly, the calculation of delay is performed for temperature values of 27˚C, 55˚C and 120˚C at 90nm technology.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

PECA

2014 ◽  
pp. 239-248
Author(s):  
Maytham Safar ◽  
Hasan Al-Hamadi ◽  
Dariush Ebrahimi
Keyword(s):  
Wireless Sensor Networks ◽  
Fault Tolerance ◽  
Sensor Networks ◽  
Power Consumption ◽  
Low Power ◽  
The Self ◽  
Wireless Sensor ◽  
Human Intervention ◽  
Electronic Circuits ◽  
Power Efficient

Wireless sensor networks (WSN) have emerged in many applications as a platform to collect data and monitor a specified area with minimal human intervention. The initial deployment of WSN sensors forms a network that consists of randomly distributed devices/nodes in a known space. Advancements have been made in low-power micro-electronic circuits, which have allowed WSN to be a feasible platform for many applications. However, there are two major concerns that govern the efficiency, availability, and functionality of the network—power consumption and fault tolerance. This paper introduces a new algorithm called Power Efficient Cluster Algorithm (PECA). The proposed algorithm reduces the power consumption required to setup the network. This is accomplished by effectively reducing the total number of radio transmission required in the network setup (deployment) phase. As a fault tolerance approach, the algorithm stores information about each node for easier recovery of the network should any node fail. The proposed algorithm is compared with the Self Organizing Sensor (SOS) algorithm; results show that PECA consumes significantly less power than SOS.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

A Low-Power and Area-Efficient 64-Bit Digital Comparator

2016 ◽  
Vol 25 (12) ◽  
pp. 1650148 ◽  
Author(s):  
N. V. Vijaya Krishna Boppana ◽  
Saiyu Ren
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Resource Sharing ◽  
Portable Devices ◽  
Worst Case ◽  
Lower Power ◽  
Digital Comparator ◽  
Area Efficient

A new low-power and area-efficient radix-4 tree-based 64-bit digital comparator is presented in this paper. The proposed design with 64 XOR-XNOR (XE) blocks is custom implemented in 90[Formula: see text]nm 1.2[Formula: see text]V multi-threshold technology using Cadence-Virtuoso layout editor. The 64 bit comparator has an area of 1009[Formula: see text][Formula: see text], a worst case delay of 858[Formula: see text]ps, and a power consumption of 898[Formula: see text]uW at 1[Formula: see text]G bit/s. The two features, lower power consumption and smaller area compared to other published comparators, make the proposed design most suitable for low-power portable devices. Resource sharing is an important feature for the proposed design. The 64 XE blocks occupy approximately 60% (600[Formula: see text][Formula: see text]) of the total comparator area and contributes 54% (484[Formula: see text][Formula: see text]W) of the total worst power consumption. The 64 XE blocks can also be used to design XE based 64-bit adders, encryption devices, etc.

Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers

2016 ◽  
Vol 25 (12) ◽  
pp. 1650149 ◽  
Author(s):  
Z. Abid ◽  
Dalia A. El-Dib ◽  
Rizwan Mudassir
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Performance ◽  
Energy Delay Product

A low power operand decomposition multiplication architecture implementation is modified to further reduce its power dissipation and delay. First, the multiplier’s implementation was modified to generate the partial products using NAND gates instead of AND and OR gates in order to reduce the number of transistors (area utilized) and to reduce the delay. Then, new types of adders and (4:2) compressors, that accept negatively weighted bits are used to reduce the number of inverters. Therefore, the resulting multiplier architecture reduces the number of transistors significantly. These modifications result in 20% and 36% reduction in power consumption and energy delay product (EDP), respectively.

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