Influence of underfill methods on the solder joint fatigue of wafer level packaging

Author(s):  
Charles Regard ◽  
Christian Gautier ◽  
Helene Fremont ◽  
Patrick Poirier
2003 ◽  
Vol 125 (4) ◽  
pp. 582-588 ◽  
Author(s):  
X. J. Zhao ◽  
G. Q. Zhang ◽  
J. F. J. M. Caers ◽  
L. J. Ernst

In this paper, an “interfacial boundary volume” based damage criterion was proposed in combination with the modified Coffin-Manson model to predict solder fatigue. This criterion assumes that mainly, the behavior of the thin solder layer at chip pad interface contributes to the solder fatigue, not the whole solder joint or the averaged strains from randomly selected elements. The damage parameter was thus calculated by averaging the visco-plastic strain range over the interfacial boundary layer volume in the solder and later related to the corresponding fatigue life of experimental test through least-squares curves fitting to determine the empirical coefficients in the Coffin-Manson equation. As a demonstrator, the solder joint fatigue in wafer level chip scale packaging under thermal shock loading was analyzed. An appropriate constitutive relation from Darveaux was used to model the inelastic deformation of the solder alloy, and the different stress-strain responses resulting from different designs were calculated. The analysis results were used to develop the empirical fatigue model based on the interfacial boundary volume damage criterion and then this fatigue model was used for prediction. The fatigue lives of chip scale packaging with variable solder land size and component size were analyzed using this model. The prediction results match well with those from experimental tests. For this demonstrator, it was also shown that the empirical model based on the interfacial boundary volume criterion was more accurate than the models obtained from other strain averaging methods.


2008 ◽  
Vol 48 (8-9) ◽  
pp. 1149-1154 ◽  
Author(s):  
Chan-Yen Chou ◽  
Tuan-Yu Hung ◽  
Shin-Yueh Yang ◽  
Ming-Chih Yew ◽  
Wen-Kun Yang ◽  
...  

2003 ◽  
Vol 125 (4) ◽  
pp. 576-581 ◽  
Author(s):  
Chang-An Yuan ◽  
Kou-Ning Chiang

Due to the CPU limitation of the computer hardware currently available, the three-dimensional full-scaled finite element model of wafer level packaging is impractical for the reliability analysis and fatigue life prediction. In order to significantly reduce the simulation CPU time, an equivalent beam method based on the micro-macro technique with multi-point constraint method is proposed in the present study. The proposed novel equivalent beam consists of three/five sections to simulate the three-dimensional solder joint with different upper/lower pad size. Moreover, the total length of the proposed equivalent beam equals to the stand-of-height of the realistic solder joint. To compare the results of equivalent beam and full-scaled model, a wafer level packaging with 48 I/O is selected as a benchmark model in this study. The result shows that the equivalent beam model can reduce approximately 80 percent CPU time, and good agreement between the equivalent beam model and the full-scaled model are achieved.


2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka

Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.


Sign in / Sign up

Export Citation Format

Share Document