A warpage of wafer level bonding for CIS (CMOS Image Sensor) device using polymer adhesive

Author(s):  
Jae-Hyun Park ◽  
Ji-Young Lee ◽  
Min-Kyo Cho ◽  
Jae-June Kim ◽  
Gu-Sung Kim
2017 ◽  
Vol 137 (2) ◽  
pp. 48-58
Author(s):  
Noriyuki Fujimori ◽  
Takatoshi Igarashi ◽  
Takahiro Shimohata ◽  
Takuro Suyama ◽  
Kazuhiro Yoshida ◽  
...  

2006 ◽  
Vol 46 (8) ◽  
pp. 1326-1334 ◽  
Author(s):  
Ching-Yang Chen ◽  
Yung-Ching Chao ◽  
De-Shin Liu ◽  
Zhen-Wei Zhuang

Sensors ◽  
2020 ◽  
Vol 20 (15) ◽  
pp. 4077
Author(s):  
Tianshen Zhou ◽  
Shuying Ma ◽  
Daquan Yu ◽  
Ming Li ◽  
Tao Hang

To meet the urgent market demand for small package size and high reliability performance for automotive CMOS image sensor (CIS) application, wafer level chip scale packaging (WLCSP) technology using through silicon vias (TSV) needs to be developed to replace current chip on board (COB) packages. In this paper, a WLCSP with the size of 5.82 mm × 5.22 mm and thickness of 850 μm was developed for the backside illumination (BSI) CIS chip using a 65 nm node with a size of 5.8 mm × 5.2 mm. The packaged product has 1392 × 976 pixels and a resolution of up to 60 frames per second with more than 120 dB dynamic range. The structure of the 3D package was designed and the key fabrication processes on a 12” inch wafer were investigated. More than 98% yield and excellent optical performance of the CIS package was achieved after process optimization. The final packages were qualified by AEC-Q100 Grade 2.


Author(s):  
Thorsten Matthias ◽  
Gerald Kreindl ◽  
Viorel Dragoi ◽  
Markus Wimplinger ◽  
Paul Lindner

2004 ◽  
Vol 44 (1) ◽  
pp. 155-161 ◽  
Author(s):  
Jong-heon Kim ◽  
In-Soo Kang ◽  
Chi-jung Song ◽  
Young-Jik Hur ◽  
Hak-Nam Kim ◽  
...  

2010 ◽  
Vol 2010 (1) ◽  
pp. 000378-000384
Author(s):  
Bioh Kim ◽  
Thorsten Matthias ◽  
Gerald Kreindl ◽  
Viorel Dragoi ◽  
Markus Wimplinger ◽  
...  

This article presents the advances in wafer-level processing and integration techniques for CMOS image sensor module manufacturing. CMOS image sensors gave birth to the low-cost, high-volume camera phone market and are being adopted for various high-end applications. The backside illumination technique has significant advantages over the front-side illumination due to separation of the optical path from the metal interconnects. Wafer bonding plays a key role in manufacturing backside illuminated sensors. The cost-effective integration of miniaturized cameras in various handheld devices becomes realized through the introduction of CMOS image sensor modules or camera modules manufactured with wafer-level processing and integration techniques. We developed various technologies enabling wafer-level processing and integration, such as (a) wafer-to-wafer permanent bonding with oxide or polymer layers for manufacturing backside illuminated sensor wafers, (b) wafer-level lens molding and stacking based on UV imprint lithography for making wafer-level optics, (c) conformal coating of various photoresists within high aspect ratio through-silicon vias, and (d) advanced backside lithography for various metallization processes in wafer-level packaging. Those techniques pave the way to the future growth of the digital imaging industry by improving the electrical and optical aspects of devices as well as the module manufacturability.


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