Noise Immune High Performance Domino Circuit Techniques for High Fan-In Logic Gate: A Review

2019 ◽

Vol 8 (6) ◽

pp. 3121-3126

Keyword(s):

Power Consumption ◽

Low Power ◽

High Performance ◽

Total Power ◽

Total Power Consumption ◽

Power Models ◽

Domino Circuit ◽

Circuit Techniques ◽

Capacitive Loading ◽

Technology Nodes

A novel modified keeper technique has been proposed in this paper for domino logic circuits implemented as wide fan in OR gate. Few circuit parameters as capacitivie loading and delay are major concerns for OR gates in deeper technology nodes. This design focuses on a comparator block with modified dual keeperto maintain the output logic state. Additionally it comprises of a delay loop to limit the contention current. The proposed design reduces the input capacitive loading and total power consumption by the circuit, while keeping the speed of operation same. It was compared with latest domino circuit techniques and the proposed design MKCD has achieved a reduction of 41% in power consumption in 64 bit configuration as compared to conventional domino circuit SFLD. Average noise immunity has also increased by more than twice as compared to SFLD. The simulations were performed using 90nm PTM low power models.

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Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

International Journal of Sensors Wireless Communications and Control ◽

10.2174/2210327909666190207163639 ◽

2020 ◽

Vol 10 (1) ◽

pp. 55-62

Author(s):

Deepika Bansal ◽

Bal Chand Nagar ◽

Brahamdeo Prasad Singh ◽

Ajay Kumar

Keyword(s):

Power Consumption ◽

High Performance ◽

Dynamic Logic ◽

Clock Frequency ◽

Charge Sharing ◽

Benchmark Circuit ◽

Domino Circuit ◽

Power Delay Product ◽

Domino Circuits ◽

Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

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A high performance 256K TTL SRAM using 0.8um triple diffused BiCMOS with 3V circuit techniques

10.1109/vlsic.1991.760057 ◽

2005 ◽

Author(s):

I. Young ◽

M. Denham ◽

J. Greason ◽

G. Kaveh ◽

J. Kolousek ◽

...

Keyword(s):

High Performance ◽

Circuit Techniques

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NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

10.21203/rs.3.rs-1130495/v1 ◽

2021 ◽

Author(s):

Yejin Yang ◽

Juhee Jeon ◽

Jaemin Son ◽

Kyoungah Cho ◽

Sangsig Kim

Keyword(s):

Processing Speed ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Silicon Nanowire ◽

Logic Gate ◽

High Energy ◽

Zero Bias ◽

Computing Systems ◽

Data Movement

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

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High Performance Energy Efficient Computation Elements of Processing Unit

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.b3964.129219 ◽

2019 ◽

Vol 9 (2) ◽

pp. 2450-2455

Keyword(s):

Energy Efficient ◽

High Performance ◽

Logic Gate ◽

Processing Unit ◽

Efficient Computation ◽

Quartus Ii ◽

Efficient Processing ◽

Exclusive Or ◽

Design Logic

in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

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