Diffusion furnace dopant activation matching through a ramped temperature idle

Author(s):  
Kevin Black
Keyword(s):  
2020 ◽  
Vol 10 (5) ◽  
pp. 1283-1289
Author(s):  
George C. Wilkes ◽  
Ajay D. Upadhyaya ◽  
Ajeet Rohatgi ◽  
Mool C. Gupta

Author(s):  
J. Borland ◽  
S. Shishiguchi ◽  
A. Mineji ◽  
W. Krull ◽  
D. Jacobson ◽  
...  
Keyword(s):  

1997 ◽  
Vol 502 ◽  
Author(s):  
A. T. Fiory

ABSTRACTThermal processing in silicon integrated circuit fabrication steps for dopant activation, metal silicides, annealing, and oxidation commonly uses single-wafer furnaces that rapidly heat wafers with incandescent infrared lamps. Radiation pyrometers and thermocouple probes are the principle methods of measuring wafer temperature for closed-loop control of rapid thermal processes. The challenge with thermocouples is in dealing with heat from the lamps and non-ideal thermally resistive wafer contact. The challenge with pyrometry is in compensating for the variable emissivity of wafer surfaces and suppressing interference from the lamps. Typical deposited or grown layers of silicon nitride, silicon dioxide, and polycrystalline silicon can produce dramatic changes in emissivity. Layer thicknesses and composition are generally not known with sufficient accuracy, so a method for real time in situ emissivity compensation is required. Accufiber introduced a “ripple technique” to address this issue. The idea is to use two probes, separately sensing radiation from the wafer and the lamps, and extracting AC and quasi-DC parts from each. The AC signals provide a measure of the reflectivity of the wafer, and thence emissivity, as well as the fraction of reflected lamp radiation present in the DC signals. Lucent Technologies introduced a method of using AC lamp ripple to measure wafer temperatures with two radiation probes at a wall in the furnace. One probe views radiation emanating from the wafer through a gap in the lamp array. The other probe has a wide field of view to include lamp radiation. The accuracy of Lucent devices, determined from process results on wafers with various emissivities, is typically in the range of 12°C to 18°C at three standard deviations.


2011 ◽  
Vol 1321 ◽  
Author(s):  
A. Kumar ◽  
P.I. Widenborg ◽  
H. Hidayat ◽  
Qiu Zixuan ◽  
A.G. Aberle

ABSTRACTThe effect of the rapid thermal annealing (RTA) and hydrogenation step on the electronic properties of the n+ and p+ solid phase crystallized (SPC) poly-crystalline silicon (poly-Si) thin films was investigated using Hall effect measurements and four-point-probe measurements. Both the RTA and hydrogenation step were found to affect the electronic properties of doped poly-Si thin films. The RTA step was found to have the largest impact on the dopant activation and majority carrier mobility of the p+ SPC poly-Si thin films. A very high Hall mobility of 71 cm2/Vs for n+ poly-Si and 35 cm2/Vs for p+ poly-Si at the carrier concentration of 2×1019 cm-3 and 4.5×1019 cm-3, respectively, were obtained.


2001 ◽  
Vol 685 ◽  
Author(s):  
Ching-Wei Lin ◽  
Li-Jing Cheng ◽  
Yin-Lung Lu ◽  
Huang-Chung Cheng

AbstractA simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.


2019 ◽  
Vol 11 (4) ◽  
pp. 11
Author(s):  
Bhavink Patel ◽  
Martin Saporito ◽  
Runye Cui ◽  
Khaled Malallah ◽  
Mohammad Alsubaiei ◽  
...  

Spin-on dopant technique has been investigated in the paper. The boron and phosphorus were used as p- and n-type dopant sources and were deposited on silicon substrates, followed by the baking process to evaporate the solvents from spin-on dopant layers. The standard drive-in process was applied to diffuse and activate the dopants. The curing temperature varied from 150 to 200 oC to investigate the temperature effect on dopant activation. It is suggested that for our selected spin-on dopant sources, the curing temperature and time of 175 oC and 60 minutes would lead to the best result of dopant activation during drive-in process, evidenced by the lowest sheet resistance, which was measured using four-point probe measurement method. 


2019 ◽  
Vol 13 (1) ◽  
pp. 45-54 ◽  
Author(s):  
Shinichi Kato ◽  
Yasuo Nara ◽  
Takayuki Aoyama ◽  
Takashi Onizawa ◽  
Yuzuru Ohji
Keyword(s):  

2006 ◽  
Vol 978 ◽  
Author(s):  
Michel Bockstedte

AbstractThe modeling of atomistic processes in semiconductors based on the density functional theory is outlined. The role of intrinsic defects in the self and dopant diffusion, as well as in the dopant activation is investigated for the case of silicon carbide. A hierarchy of annealing mechanisms for vacancies and interstitials is proposed. The identification of the microscopic origin of experimental defect centers by calculated defect signatures establishes a link between theoretical modeling and experiments.


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