Accurate modeling of dynamic variability of SRAM cell in 28 nm FDSOI technology

2014 ◽  
Author(s):  
J. El Husseini ◽  
A. Subirats ◽  
X. Garros ◽  
A. Makoseij ◽  
O. Thomas ◽  
...  
Keyword(s):  
Sram Cell ◽  
28 Nm

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

2019 ◽  
Vol 29 (06) ◽  
pp. 2050095
Author(s):  
Chua-Chin Wang ◽  
Zong-You Hou ◽  
Deng-Shian Wang ◽  
Chia-Lung Hsieh
Keyword(s):  
Power Supply ◽  
Process Variation ◽  
Half Period ◽  
Clock Rate ◽  
System Clock ◽  
Sram Cell ◽  
Sram Design ◽  
Measurement Results ◽  
Power Delay Product ◽  
28 Nm

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

2017 ◽  
Vol 64 (9) ◽  
pp. 2438-2447 ◽  
Author(s):  
Anuj Grover ◽  
G. S. Visweswaran ◽  
Chittoor R. Parthasarathy ◽  
Mohammad Daud ◽  
David Turgis ◽  
...  
Keyword(s):  
Sram Cell ◽  
28 Nm

Combining Current Imaging, EBIC/EBAC, and Electrical Probing for Fast and Reliable In-Situ Electrical Fault Isolation

2016 ◽  
Author(s):  
Stephan Kleindiek ◽  
Matthias Kemmler ◽  
Andreas Rummel ◽  
Klaus Schock
Keyword(s):  
Imaging Technique ◽  
Fault Isolation ◽  
28 Nm

Abstract Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28 nm samples inside an SEM. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults.

A New Approach for SRAM Soft Defect Root Cause Identification

2007 ◽  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger
Keyword(s):  
Integrated Circuits ◽  
Top Down ◽  
Feature Size ◽  
Design Rules ◽  
New Approach ◽  
Root Cause ◽  
Wafer Fab ◽  
Sram Cell ◽  
Tcad Simulation ◽  
Root Cause Identification

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

High Speed 1-tap Decision Feedback Equalizer in 28 nm CMOS

2014 ◽  
Vol 9 (9th) ◽  
pp. 1-12
Author(s):  
Mostafa Hosny ◽  
Sameh Ibrahim ◽  
DiaaEldin Khalil ◽  
Mohamed Dessouky
Keyword(s):  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
28 Nm
Sign in / Sign up

Export Citation Format

Share Document