A low-noise low-voltage low-power bulk-driven amplifier with chopper stabilization technique

Author(s):  
Zhipeng Xiang ◽  
Huajun Fang ◽  
Tong Ling ◽  
Xiao Zhao ◽  
Jun Xu
Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1157 ◽  
Author(s):  
Robert Chebli ◽  
Mohamed Ali ◽  
Mohamad Sawan

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .


2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.


2019 ◽  
Author(s):  
Qisheng Zhang ◽  
Wenhao Li ◽  
Feng Guo ◽  
Zhenzhong Yuan ◽  
Shuaiqing Qiao ◽  
...  

Abstract. In the past few decades, with the continuous advancement of technology, seismic-electrical instruments have developed rapidly. However, complex and harsh exploration environments have put forward higher requirements and severe challenges for traditional geophysical exploration methods and instruments. Therefore, it is extremely urgent to develop new high-precision exploration instruments and data acquisition systems. In this study, a new distributed seismic-electrical hybrid acquisition station is developed using system-on-a-programmable-chip (SoPC) technology. The acquisition station hardware includes an analog board and a main control board. The analog board uses a signal conditioning circuit and a 24-bit analog-to-digital converter (ADS1271) to achieve high-precision data acquisition, while the main control board uses a low-power SoPC chip to enable high-speed stable data transmission. Moreover, the data transmission protocol for the acquisition station was designed, an improved low-voltage differential signaling data transmission technology was independently developed, and a method to enhance the precision of synchronous acquisition was studied in depth. These key technologies, which were developed for the acquisition station, were integrated into the SoPC of the main control board. Testing results indicate that the synchronization precision of the acquisition station is better than 200 ns, and the maximum low-power data transmission speed is 16 Mbps along a 55 m cable. Simultaneously, the developed acquisition station has the advantages of low noise, large dynamic range, low power consumption, etc., and it can achieve high-precision hybrid acquisition of seismic-electrical data.


2011 ◽  
Vol 483 ◽  
pp. 508-512
Author(s):  
Hai Xi Lu ◽  
Yong Ping Xu ◽  
Shou Rong Wang

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.


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