Correction to “A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique” [Dec 09 2533-2543]

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.

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Low-noise, low-offset modulator demodulator circuit for chopper stabilization technique in CMOS-MEMS sensor applications

2014 5th International Conference on Intelligent and Advanced Systems (ICIAS) ◽

10.1109/icias.2014.6869473 ◽

2014 ◽

Cited By ~ 3

Author(s):

N. Y. Sutri ◽

J. O. Dennis ◽

M. H. Md. Khir ◽

T. B. Tang ◽

M. U. Mian

Keyword(s):

Low Noise ◽

Sensor Applications ◽

Chopper Stabilization ◽

Mems Sensor ◽

Cmos Mems ◽

Stabilization Technique ◽

Low Offset

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High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems

Electronics ◽

10.3390/electronics8101157 ◽

2019 ◽

Vol 8 (10) ◽

pp. 1157 ◽

Cited By ~ 1

Author(s):

Robert Chebli ◽

Mohamed Ali ◽

Mohamad Sawan

Keyword(s):

Low Noise ◽

Common Mode ◽

Fully Integrated ◽

Dc Offset ◽

Chopper Stabilization ◽

Logarithmic Amplifier ◽

Offset Voltage ◽

High Cmrr ◽

Programmable Gain ◽

Stabilization Technique

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .

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