Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits

With rapid technology scaling down, the energy dissipation of nanometer CMOS circuits is becoming a major concern, because of the increasing sub-threshold leakage in nanometer CMOS processes. This paper introduces a dual threshold CMOS (DTCMOS) technique for CPAL (complementary pass-transistor adiabatic logic) circuits to reduce sub-threshold leakage dissipations. The method to size the transistors of the dual-threshold CPAL gates is also discussed. A full adder using dual-threshold CPAL circuits is realized using 45nm BSIM4 CMOS model. HSPICE simulation results show that leakage dissipations of the CPAL full adder with DTCMOS techniques are reduced compared with the basic CPAL one.

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Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

Science China Information Sciences ◽

10.1007/s11432-013-5051-y ◽

2014 ◽

Vol 57 (4) ◽

pp. 1-13 ◽

Cited By ~ 2

Author(s):

Kai Liao ◽

XiaoXin Cui ◽

Nan Liao ◽

KaiSheng Ma ◽

Di Wu ◽

...

Keyword(s):

Low Power ◽

Power Dissipation ◽

Logic Circuits ◽

Ultra Low Power ◽

Adiabatic Logic ◽

Low Power Dissipation ◽

Pass Transistor

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Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.121-122.97 ◽

2010 ◽

Vol 121-122 ◽

pp. 97-102 ◽

Cited By ~ 3

Author(s):

Wei Qiang Zhang ◽

Li Su ◽

Li Fang Ye ◽

Jian Ping Hu

Keyword(s):

Power Dissipation ◽

Low Power Design ◽

Logic Circuits ◽

Leakage Power ◽

Nanometer Cmos ◽

Wide Range ◽

Adiabatic Logic ◽

Total Leakage ◽

Pass Transistor ◽

Simulation Results

The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.

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