Voltage Scaling for Adiabatic Register File Based on Complementary Pass-Transistor Adiabatic Logic

2011 ◽  
pp. 39-46
Author(s):  
Haiyan Ni ◽  
Xiaolei Sheng ◽  
Jianping Hu
Keyword(s):  
Voltage Scaling ◽  
Register File ◽  
Adiabatic Logic ◽  
Pass Transistor

A NOVEL ADIABATIC REGISTER FILE DESIGN

2000 ◽  
Vol 10 (01n02) ◽  
pp. 67-76 ◽  
Author(s):  
K. W. NG ◽  
K. T. LAU
Keyword(s):  
Power Consumption ◽  
Register File ◽  
Adiabatic Switching ◽  
Adiabatic Logic ◽  
File Design ◽  
Pass Transistor ◽  
Simulation Results ◽  
Cmos Implementation ◽  
Large Capacitance ◽  
Hspice Simulation

A novel 8-word × 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-down configuration (PAL-2N). Using adiabatic switching technique, the power consumption of the register file is significantly reduced as the energy transferred to the large capacitance buses is mostly recovered. HSPICE simulation results have shown power savings of more than 77% as compared to the conventional CMOS implementation. Although the proposed register file is designed with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.

scholarly journals Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

VLSI Design ◽  
2013 ◽  
Vol 2013 ◽  
pp. 1-9 ◽  
Author(s):  
A. Kishore Kumar ◽  
D. Somasundareswari ◽  
V. Duraisamy ◽  
T. Shunbaga Pradeepa
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Full Adder ◽  
Double Pass ◽  
Voltage Level ◽  
Circuit Performance ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Implementation ◽  
Low Power Multiplier

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration

2010 ◽  
Vol 39 ◽  
pp. 73-78 ◽  
Author(s):  
Jin Tao Jiang ◽  
Li Fang Ye ◽  
Jian Ping Hu
Keyword(s):  
Gate Oxide ◽  
Cmos Process ◽  
Oxide Materials ◽  
Gate Leakage ◽  
Leakage Reduction ◽  
Nanometer Cmos ◽  
Benchmark Circuit ◽  
Adiabatic Logic ◽  
Pass Transistor ◽  
Cmos Processes

Leakage power reduction is extremely important in the design of nano-circuits. Gate leakage has become a significant component in currently used nanometer CMOS processes with gate oxide structure. The structure and operation of the PAL-2P (pass-transistor adiabatic logic with PMOS pull-up configuration) circuits that consist mostly of PMOS transistors are complementary to PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) ones that consist mostly of NMOS transistors. This paper investigates gate leakage reduction of the PAL-2P circuits in nanometer CMOS processes with gate oxide materials. An s27 benchmark circuit from the ISCAS89 sequential benchmark set is verified using the PAL-2P scheme. All circuits are simulated with HSPICE using the 65nm CMOS process with gate oxide materials. Based on the power dissipation models of PAL-2P adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations using SPICE simulations. The PAL-2P circuits consume low static power compared with traditional PAL-2N ones.

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