A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

2003 ◽  
Author(s):  
S. Thompson ◽  
N. Anand ◽  
M. Armstrong ◽  
C. Auth ◽  
B. Arcot ◽  
...  
Keyword(s):  
Strained Silicon ◽  
Cu Interconnects ◽  
Sram Cell ◽  
Low K

Electromigration failure mode concerning negative resistance shift of Cu interconnects buried in porous low-k dielectric

2017 ◽  
Vol 110 (8) ◽  
pp. 083502 ◽  
Author(s):  
Hui Zheng ◽  
Binfeng Yin ◽  
Hewei Yu ◽  
Leigang Chen ◽  
Lin Gao ◽  
...  
Keyword(s):  
Failure Mode ◽  
Negative Resistance ◽  
Cu Interconnects ◽  
Low K

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

2016 ◽  
Vol 5 (10) ◽  
pp. P578-P583 ◽  
Author(s):  
Naoki Torazawa ◽  
Susumu Matsumoto ◽  
Takeshi Harada ◽  
Yasunori Morinaga ◽  
Daisuke Inagaki ◽  
...  
Keyword(s):  
High Performance ◽  
Hard Mask ◽  
Integration Technology ◽  
Cu Interconnects ◽  
Low K

scholarly journals Electrical and Reliability Characteristics of Self-Forming Barrier for CuNd/SiOCH Films in Cu Interconnects

Coatings ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 155
Author(s):  
Yi-Lung Cheng ◽  
Chih-Yen Lee ◽  
Wei-Fan Peng ◽  
Giin-Shan Chen ◽  
Jau-Shiung Fang
Keyword(s):  
Dielectric Film ◽  
Alloy Film ◽  
Dielectric Films ◽  
Low Dielectric Constant ◽  
Electrical Characteristics ◽  
Sputtering Deposition ◽  
Cu Interconnects ◽  
Low Dielectric ◽  
Reliability Characteristics ◽  
Low K

In this study, Cu-2.2 at. % Nd alloy films using a co-sputtering deposition method were directly deposited onto porous low-dielectric-constant (low-k) films (SiOCH). The effects of CuNd alloy film on the electrical properties and reliability of porous low-k dielectric films were studied. The electrical characteristics and reliability of the porous low-k dielectric film with CuNd alloy film were enhanced by annealing at 425 °C. The formation of self-forming barrier at the CuNd/SiOCH interface was responsible for this improvement. Therefore, integration with CuNd and porous low-k dielectric is a promising process for advanced Cu interconnects.

Effect of Via-Profile on the Via Reliability in Scaled-down Low-k/Cu Interconnects

2009 ◽  
Author(s):  
I. Kume ◽  
N. Inoue ◽  
S. Saito ◽  
N. Furutake ◽  
J. Kawahara ◽  
...  
Keyword(s):  
Cu Interconnects ◽  
Down Low ◽  
Low K

Improvement of Variability and Reliability in Low-k/Cu Interconnects by Selectivity Control in Dry-Etching Process

2010 ◽  
Author(s):  
I. Kume ◽  
M. Ueki ◽  
N. Inoue ◽  
J. Kawahara ◽  
N. Ikarashi ◽  
...  
Keyword(s):  
Dry Etching ◽  
Etching Process ◽  
Cu Interconnects ◽  
Selectivity Control ◽  
Low K
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