CMOS device design and optimization from a perspective of circuit-level energy-delay optimization
2019 ◽
Vol 7
(3)
◽
pp. 1440-1448
◽
2021 ◽
2008 ◽
Vol 55
(1)
◽
pp. 152-162
◽
2018 ◽
Vol 108
◽
pp. 032021
◽
2008 ◽
Vol 55
(2)
◽
pp. 609-615
◽