scholarly journals Investigation of Variation in Device Design Parameters on the Saturation Voltages of Hetero-junction Nanowire Tunnel FETs

2021 ◽  
Author(s):  
Abhishek Acharya
Keyword(s):  
Channel Length ◽  
Design Parameters ◽  
Device Design ◽  
Short Channel ◽  
Nanowire Diameter ◽  
Saturation State ◽  
Design And Optimization ◽  
Optimization Parameters ◽  
Tunnel Fets ◽  
The Impact

Abstract Estimation of the saturation voltages of beyond CMOS devices is essential for the accurate circuit design and analysis. In this work, we look at the influence of device design parameters on the saturation voltage (VDSAT) of a Tunnel Field Effect Transistor (TFET) using 3D TCAD Numerical Simulations. The variation in channel length, underlap at gate-drain, source/drain doping, and the source/channel material are some of the vital optimization parameters in the design and optimization of TFET based circuits. We observe, with the increasing value of drain bias (VDS), TFET device initially enters in the soft saturation state and subsequently a deep saturation state is attained. These voltages are altered with device variability and hence the analog performance. An increase in drain (source) doping increases (decreases) the soft saturation voltage of TFETs. It is also found that an early onset of saturation can be achieved by the gate-drain underlap in TFETs. The impact of short channel lengths is to worsen the perfect saturation phenomenon in Tunnel FETs. In addition, the reduction in nanowire diameter delays the saturation by few milivolts.

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

scholarly journals A one-dimensional model for tidal array design based on three-scale dynamics

2017 ◽  
Vol 825 ◽  
pp. 651-676 ◽  
Author(s):  
Vikrant Gupta ◽  
Anna M. Young
Keyword(s):  
Surface Deformation ◽  
Channel Length ◽  
Design Parameters ◽  
Tidal Channels ◽  
Tidal Current Energy ◽  
Array Design ◽  
One Dimensional ◽  
Power Extraction ◽  
The Impact ◽  
Current Energy

In order to make the extraction of tidal current energy economically viable, the power production per turbine must be optimised in each tidal array. Furthermore, the impact of power extraction on the marine flow environment must be understood. These two aims mean that designers must be able to model different configurations of a tidal array in order to create the most efficient, least invasive arrangement. In this paper, an analytical model is developed for array design in idealised rectangular tidal channels with idealised turbines. The model includes the effects of (i) local blockage, (ii) surface deformation and (iii) added drag due to the installation of the array. While these effects have been accounted for individually in past work, the model presented here is the first to include all three such that the interaction between different effects can be understood. Results are presented for optimal local blockage and turbine resistance as functions of inherent channel drag coefficient, channel length and Froude number at various global blockage values. It will be shown that it is necessary to model the effects of local blockage and added drag simultaneously in order to obtain the design parameters of a tidal array (global blockage, local blockage and turbine resistance), which will maximise the power extraction per turbine. Neglecting either effect will lead to an array design with lower power extraction than the optimum, the addition of unnecessary extra turbines and higher lost power from the array.

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

2017 ◽  
Vol 27 (04) ◽  
pp. 1850063 ◽  
Author(s):  
Rajneesh Sharma ◽  
Rituraj S. Rathore ◽  
Ashwani K. Rana
Keyword(s):  
Dielectric Materials ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
The Impact ◽  
Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

Three Dimensional Design and Optimization of a Transonic Rotor in Axial Flow Compressors

2011 ◽  
Author(s):  
Hidetaka Okui ◽  
Tom Verstraete ◽  
R. A. Van den Braembussche ◽  
Zuheyr Alsalihi
Keyword(s):  
Three Dimensional ◽  
Axial Flow ◽  
Design Parameters ◽  
Negative Effects ◽  
Stall Margin ◽  
Design And Optimization ◽  
Transonic Compressor ◽  
Compressor Rotor ◽  
Differential Evolutionary Algorithm ◽  
The Impact

This paper presents a 3-D optimization of a moderately loaded transonic compressor rotor by means of a multi-objective optimization system. The latter makes use of a Differential Evolutionary Algorithm in combination with an Artificial Neural Network and a 3D Navier-Stokes solver. Operating it on a cluster of 30 processors enabled the optimization of a large design space composed of the tip camber line and spanwise distribution of sweep and chord length. Objectives were an increase of efficiency at unchanged stall margin by controlling the shock waves and off-design performance curve. First, tests on a single blade row allowed a better understanding of the impact of the different design parameters. Forward sweep with unchanged camber improved the peak efficiency by only 0.3% with a small increase of the stall margin. Backward sweep with an optimized S shaped camber line improved the efficiency by 0.6% with unchanged stall margin. It is explained how the camber line control could introduce the forward sweep effect and compensate the negative effects of the backward sweep. The best results (0.7% increase in efficiency and unchanged stall margin) have been obtained by a stage optimization that also considered the spanwise redistribution of the rotor flow and loading to reduce the Mach number at the stator hub.

scholarly journals New Method for Determination of Drain Saturation Voltage in Short Channel MOS Devices Between Liquid Helium to Room Temperature

2001 ◽  
Vol 24 (2) ◽  
pp. 129-134
Author(s):  
Y. Amhouche ◽  
A. El Abbassi ◽  
K. Raïs ◽  
E. Bendada ◽  
R. Rmaily
Keyword(s):  
Room Temperature ◽  
Impact Ionization ◽  
Ionization Rate ◽  
Channel Length ◽  
New Method ◽  
Short Channel ◽  
Mos Devices ◽  
Impact Ionization Rate ◽  
The Impact

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.

Design Considerations for Robust Manufacturing and High Yield of 1.2 kV 4H-SiC VDMOS Transistors

2019 ◽  
Vol 963 ◽  
pp. 763-767
Author(s):  
Holger Schlichting ◽  
Tomasz Sledziewski ◽  
Anton Bauer ◽  
Tobias Erlbacher
Keyword(s):  
High Performance ◽  
Electrical Characteristic ◽  
Semiconductor Device ◽  
Critical Length ◽  
Channel Length ◽  
High Yield ◽  
Short Channel ◽  
Channel Effects ◽  
Small Change ◽  
The Impact

Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.

Theory of Vertical Amorphous Silicon Thin-Film Transistors

1989 ◽  
Vol 149 ◽  
Author(s):  
J. G. Shaw ◽  
M. Hack
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistor ◽  
Channel Length ◽  
Large Area ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Design And Optimization ◽  
Current Path ◽  
Output Characteristics

ABSTRACTWe describe a vertical amorphous silicon thin-film transistor which is easy to fabricate and has a very short channel length that is determined by deposition, not lithography. Our vertical TFTs are compatible with large-area processing techniques andd have suitable terminal characteristics for use in practical circuits. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. We show how to suppress excessive leakage currents and improve the saturation of the output characteristics by a novel current-blocking technique.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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