Over Kilovolt GaN Vertical Super-Junction Trench MOSFET: Approach for Device Design and Optimization

Author(s):  
Peng Huang ◽  
Qi Zhou ◽  
Kuangli Chen ◽  
Xiaoqi Han ◽  
Dong Wei ◽  
...  
Author(s):  
Qi Zhou ◽  
Peng Huang ◽  
Yuanyuan Shi ◽  
Kuangli Chen ◽  
Dong Wei ◽  
...  

2021 ◽  
Author(s):  
Abhishek Acharya

Abstract Estimation of the saturation voltages of beyond CMOS devices is essential for the accurate circuit design and analysis. In this work, we look at the influence of device design parameters on the saturation voltage (VDSAT) of a Tunnel Field Effect Transistor (TFET) using 3D TCAD Numerical Simulations. The variation in channel length, underlap at gate-drain, source/drain doping, and the source/channel material are some of the vital optimization parameters in the design and optimization of TFET based circuits. We observe, with the increasing value of drain bias (VDS), TFET device initially enters in the soft saturation state and subsequently a deep saturation state is attained. These voltages are altered with device variability and hence the analog performance. An increase in drain (source) doping increases (decreases) the soft saturation voltage of TFETs. It is also found that an early onset of saturation can be achieved by the gate-drain underlap in TFETs. The impact of short channel lengths is to worsen the perfect saturation phenomenon in Tunnel FETs. In addition, the reduction in nanowire diameter delays the saturation by few milivolts.


Author(s):  
Boli Peng ◽  
Manojkumar Annamalai ◽  
Sven Mothes ◽  
Michael Schröter

AbstractCarbon nanotube (CNT) field-effect transistors (FETs) have recently reached high-frequency (HF) performance similar to that of silicon RF-CMOS at the same gate length despite a tube density and current per tube that are far from the physical limits and suboptimal device architecture. This work reports on an investigation of the optimal device design for practical HF applications in terms of cut-off frequencies, power gain, and linearity. Different fundamental designs in the gate contact arrangement are considered based on a 3D device simulation of both CNTs and contacts. First, unit cells with a single CNT and minimal contact sizes are compared. The resulting simulation data are then extended toward a structure with two gate fingers and realistic contact sizes. Corresponding parasitic capacitances, as well as series and contact resistances, have been included for obtaining realistic characteristics and figures of merit that can be used for comparison with corresponding silicon RF MOSFETs. Finally, a sensitivity analysis of the device architecture with the highest performance is performed in order to find the optimal device design space.


1998 ◽  
Vol 507 ◽  
Author(s):  
Hong Zhu ◽  
Stephen J Fonash

ABSTRACTComputer device transport simulation can be a very powerful tool for device physics understanding, design, and optimization. This is especially true when it is done with a PC version that can be easily run on the desktop. However, like any powerful tool, computer simulation must be used with care and appreciation. Using our newest version of our AMPS (Analysis of Microelectronic and Photonic Structures) [1,2] transport physics code, AMPS for Windows 95/NT, we discuss using solar cell simulations for increased understanding, for materials evaluation, and for device design and optimization.


Author(s):  
Feng Zhang ◽  
Haitao Li ◽  
Na Li ◽  
Nan Zhang ◽  
Wei Lv ◽  
...  

2008 ◽  
Vol 55 (2) ◽  
pp. 609-615 ◽  
Author(s):  
C. R. Manoj ◽  
Meenakshi Nagpal ◽  
Dhanya Varghese ◽  
V. Ramgopal Rao

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