Analysis of leakage power reduction techniques in digital circuits

2011 ◽  
Author(s):  
Anup Jalan ◽  
Mamta Khosla
Keyword(s):  
Digital Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Reduction Techniques

scholarly journals Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

2017 ◽  
Vol 14 (1) ◽  
pp. 74 ◽  
Author(s):  
B. Kalagadda ◽  
N. Muthyala ◽  
K.K. Korlapati
Keyword(s):  
Power Dissipation ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Performance Comparison ◽  
Power Reduction ◽  
Leakage Power ◽  
Nand Gate ◽  
Reduction Techniques ◽  
Half Adder ◽  
Subthreshold Leakage

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation. 

scholarly journals POWER REDUCTION BY GUARDED EVALUATION CONSIDERING LOGIC ARCHITECTURE AND USING CLOCK GATING

2015 ◽  
pp. 233-238
Author(s):  
G. SURESH ◽  
A.RAM KUMAR
Keyword(s):  
Digital Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Reduction Technique ◽  
Digital Design ◽  
Combinational Circuits ◽  
Clock Gating ◽  
Dynamic Power ◽  
Circuit Input

In this paper, guarded evaluation is a dynamic power reduction technique by identifying sub circuits inputs and kept constant at specific times during circuit operation. In certain condition, some signals within the digital design are not observable at output. So make such signals as guarded (constant). There by reducing the dynamic power. Here we apply this technique for all digital circuits. The problem here is to find conditions under which a sub circuit input can be held constant with disturbing the main circuit functionally (correctness). Here we propose a solution for discovering the gating inputs based on inverting and non-inverting methods. By including “clock gating” we still reduce the dynamic power and leakage power especially for sequential circuits and also used to some small combinational circuits.

scholarly journals An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits

2014 ◽  
Vol 94 (7) ◽  
pp. 24-28
Author(s):  
Manikya VaraPrasadDone ◽  
Uday Panwar ◽  
Kavita Khare
Keyword(s):  
Digital Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Cmos Vlsi

scholarly journals Comparison of Leakage Power Reduction Techniques in 65nm Technologies

2016 ◽  
Vol 134 (8) ◽  
pp. 28-32
Author(s):  
Vikas Singhai ◽  
Saima Ayyub ◽  
Paresh Rawat
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Reduction Techniques

scholarly journals Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications

2012 ◽  
Vol 30 ◽  
pp. 1163-1170 ◽  
Author(s):  
M.Geetha Priya ◽  
K. Baskaran ◽  
D. Krishnaveni
Keyword(s):  
Deep Submicron ◽  
Power Reduction ◽  
Leakage Power ◽  
Reduction Techniques
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