scholarly journals Exploiting parallelism to boost data-path rate in high-speed IP/MPLS networking

2004 ◽  
Author(s):  
Indra Widjaja ◽  
A.I. Elwalid
Keyword(s):  
High Speed ◽  
Data Path

scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

scholarly journals An overview of the MATHILDA system

1974 ◽  
Vol 3 (34) ◽  
Author(s):  
Peter Kornerup ◽  
Bruce D. Shriver
Keyword(s):  
High Speed ◽  
Design Research ◽  
Data Path ◽  
Processor Design ◽  
Local Storage

A dynamically microprogrammable processor called MATHILDA is described. MATHILDA has been designed to be used as a tool in emulator and processor design research. It has a very general microinstruction sequencing scheme, sophisticated masking and shifting capability, high speed local storage, a 64-bit wide main data path, a horizontalty encoded microinstruction, and other facilities which make it reasonably well suited for this purpose. This paper presents an overview of the MATHILDA system.

A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications

2021 ◽  
pp. 2250049
Author(s):  
Uppugunduru Anil Kumar ◽  
G. Sahith ◽  
Sumit K Chatterjee ◽  
Syed Ershad Ahmed
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Computational Error ◽  
Data Path ◽  
Computation Complexity ◽  
Image Smoothing ◽  
Error Resilient ◽  
Power Efficient ◽  
Similar Work

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

Testing a High-Speed Data Path The Design of the RSAβ Crypto Chip

1996 ◽  
pp. 728-743
Author(s):  
Wolfgang Mayerwieser ◽  
Karl C. Posch ◽  
Reinhard Posch ◽  
Volker Schindler
Keyword(s):  
High Speed ◽  
Data Path ◽  
High Speed Data

scholarly journals High speed modified carry save adder using a structure of multiplexers

2021 ◽  
Vol 11 (2) ◽  
pp. 1591
Author(s):  
Ahmed Salah Hameed ◽  
Marwa Jawad Kathem
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Thermal Power ◽  
Software Tool ◽  
Full Adder ◽  
Data Path ◽  
Efficient Design ◽  
Worst Case ◽  
Average Improvement ◽  
Quartus Ii

Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

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