A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications

2021 ◽  
pp. 2250049
Author(s):  
Uppugunduru Anil Kumar ◽  
G. Sahith ◽  
Sumit K Chatterjee ◽  
Syed Ershad Ahmed
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Computational Error ◽  
Data Path ◽  
Computation Complexity ◽  
Image Smoothing ◽  
Error Resilient ◽  
Power Efficient ◽  
Similar Work

Most image processing applications are naturally imprecise and can tolerate computational error up to a specific limit. In such applications, savings in power are achieved by pruning the data path units, such as an adder module. Truncation, however, may lead to errors in computing, and therefore, it is always a challenge between the amount of error that can be tolerated in an application and savings achieved in area, power and delay. This paper proposes a segmented approximate adder to reduce the computation complexity in error-resilient image processing applications. The sub-carry generator aids in achieving a faster design while carry speculation method employed improves the accuracy. Synthesis results indicate a reduced die-area up to 36.6%, improvement in delay up to 62.9%, and reduction in power consumption up to 34.1% compared to similar work published previously. Finally, the proposed adder is evaluated by using image smoothing and sharpening techniques. Simulations carried out on these applications prove that the proposed adder obtains better peak signal-to-noise ratio than those available in the literature.

A Novel Efficient CNFET-Based Inexact Full Adder Design for Image Processing Applications

2021 ◽  
pp. 2150016
Author(s):  
Yavar Safaei Mehrabani ◽  
Mona Parsapour ◽  
Mona Moradi ◽  
Mehdi Bagherizadeh
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Full Adder ◽  
Propagation Delay ◽  
Arithmetic Circuits ◽  
Power Supplies ◽  
Error Resilient ◽  
High Speed Design

Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector

2017 ◽  
Vol 26 (05) ◽  
pp. 1750082 ◽  
Author(s):  
Yavar Safaei Mehrabani ◽  
Reza Faghih Mirzaee ◽  
Zahra Zareei ◽  
Seyedeh Mohtaram Daryabari
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Field Effect Transistors ◽  
Signal To Noise Ratio ◽  
Full Adder ◽  
Motion Detector ◽  
Processing Application ◽  
Image Processing Application ◽  
Area Occupation ◽  
Error Distance

This paper presents a novel inexact full adder based on carbon nanotube field-effect transistors (CNTFET) for approximate computations, which has soared in popularity especially for image processing applications. The proposed design generates the output carry without error. Therefore, the propagation of incorrect value to higher bit positions is avoided. It has the least relative error distance (Relative ED) compared to other approximate full adders reported in the literature. Practical simulations by using MATLAB demonstrate higher peak signal to noise ratio (PSNR) and image quality for motion detector image processing application. HSPICE simulations also confirm the efficiency of the proposed design. Moreover, area occupation is investigated by using electric tool. Power consumption, delay, area and ED are important evaluating factors in this subject. Comparisons are made by a comprehensive parameter (PDAEDP), based on which the new design has 23.8%, 41.5%, 70.5%, 78% and 83.6% higher performance than TGA1, TGA2, AXA1, AXA2 and AXA3, respectively.

scholarly journals Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

2022 ◽  
Author(s):  
Nelson Kingsley Joel Peter Thiagarajan ◽  
Vijeyakumar K N ◽  
Saravanakumar S
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Filter Design ◽  
Parallel Architecture ◽  
Approximate Computing ◽  
Error Resilient ◽  
Trade Off ◽  
Power Efficient ◽  
Precise Estimation ◽  
Power Delay Product

Abstract Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.

scholarly journals A LOW POWER AND HIGH SPEED APPROXIMATE ADDER FOR IMAGE PROCESSING APPLICATIONS

2021 ◽  
Vol 9 ◽  
Author(s):  
Dr.Narmadha G ◽  
◽  
Dr.Deivasigamani S ◽  
Dr.Balasubadra K ◽  
Mr.Selvaraj M ◽  
...  
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Processing System ◽  
Digital Signal ◽  
Vital Role ◽  
Human Beings ◽  
Signal Processing System ◽  
Power Efficient

Low power is an essential requirement for suitable multimedia devices, image compression techniques utilizing several signal processing architectures and algorithms. In numerous multimedia applications, human beings are able to congregate practical information from somewhat erroneous outputs. Therefore, exact outputs are not necessary to produce. In Digital signal processing system, adders play a vital role as an arithmetic module in fixing the power and area utilization of the system. The trade off parameters such as area, time and power utilization also the fault tolerance environment of few applications have employed as a base for the adverse development and use of approximate adders. In this paper, various types of existing adders, approximate adders are analyzed based on the area, delay and power consumption. Also an approximate, high speed and power efficient adder is proposed which yields the better performance than the existing adders. It can be used in various image processing applications, data mining and where the accurate outputs are not needed. The existing and proposed approximate adders are simulated by using Xilinx ISE for time and area utilization. Power simulation has been done by using Microwind Software.

HIGH-SPEED OBSERVATIONS OF HIGHLY EROSIVE VORTEX CAVITATION USING IMAGE PROCESSING

1995 ◽  
Vol 2 (2) ◽  
pp. 161-172 ◽  
Author(s):  
Kohtaro Ohba ◽  
Hitoshi Soyama ◽  
Sho Takeda ◽  
Hikaru Inooka ◽  
Risaburo Oba
Keyword(s):  
Image Processing ◽  
High Speed

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

40 Gb/s High-speed mode-division multiplexing transmission employing NRZ modulation format

2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Rabiu Imam Sabitu ◽  
Nafizah Goriman Khan ◽  
Amin Malekmohammadi
Keyword(s):  
System Performance ◽  
High Speed ◽  
Direct Detection ◽  
Signal To Noise Ratio ◽  
Optical Signal ◽  
Threshold Power ◽  
Modulation Format ◽  
Transmission Distance ◽  
Mode Division Multiplexing ◽  
Speed Mode

AbstractThis report examines the performance of a high-speed MDM transmission system supporting four nondegenerate spatial modes at 10 Gb/s. The analysis adopts the NRZ modulation format to evaluate the system performance in terms of a minimum power required (PN) and the nonlinear threshold power (PTH) at a BER of 10−9. The receiver sensitivity, optical signal-to-noise ratio, and the maximum transmission distance were investigated using the direct detection by employing a multimode erbium-doped amplifier (MM-EDFA). It was found that by properly optimizing the MM-EDFA, the system performance can significantly be improved.

Sign in / Sign up

Export Citation Format

Share Document