scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

scholarly journals Design of High-Speed Adders for Efficient Digital Design Blocks

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Deepa Yagain ◽  
Vijaya Krishna A ◽  
Akansha Baliga
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Digital Design ◽  
Data Path ◽  
Lattice Filter ◽  
Cmos Design ◽  
Addition Problem ◽  
Parallel Prefix ◽  
Prefix Adders

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

scholarly journals A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay

IJOSTHE ◽  
2020 ◽  
Vol 7 (1) ◽  
pp. 4
Author(s):  
Rimjhim Saxena ◽  
Kiran Sharma
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Compact Size ◽  
Comparative Review ◽  
Basic Functions ◽  
The One

Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

2021 ◽  
Vol 9 (9) ◽  
pp. 66-70
Author(s):  
Nakul C. Kubsad
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Digital Signal Processors ◽  
Transmission Gate ◽  
Logical Operations ◽  
Recent Advancement ◽  
Voltage Swing ◽  
Signal Processors

Abstract: Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.

scholarly journals Detection and control of a gyroscopically induced vibration to improve the balance of a single-wheel robot

2017 ◽  
Vol 37 (3) ◽  
pp. 443-455 ◽  
Author(s):  
Sangdeok Lee ◽  
Seul Jung
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Balance Control ◽  
A Priori ◽  
Experimental Studies ◽  
Notch Filter ◽  
Digital Signal ◽  
Control Performance ◽  
And Control ◽  
Balancing Control

In this article, an experimental investigation of the detection of a gyroscopically induced vibration and the balancing control performance of a single-wheel robot is presented. The balance of the single-wheel robot was intended to be maintained by virtue of the gyroscopic effect induced from a highly rotating flywheel. Since the flywheel rotates at a high speed, an asymmetrical structure of a flywheel causes an irregular rotation and becomes one of the major vibration sources. A vibration was detected and suppressed a priori before applying control algorithms to the robot. Gyroscopically induced vibrations can empirically be detected with different rotational velocities. The detection of the balancing angle of the single-wheel robot was accomplished by using an attitude and heading reference system. After identifying the vibrating frequencies, a notch filter was designed to suppress the vibration at the typical frequencies identified through experiments. A digital filter was designed and implemented in a digital signal processor(DSP) along with the control scheme for the balance control performance. The performance of the proposed method was verified by the experimental studies on the balancing control of the single-wheel robot. Experimental results confirmed that the notch filter designed following the detection of the flywheel’s vibration actually improved the balancing control performance. A half of the vibration magnitude was reduced by the proposal.

A Polarization Stabilization Control System Based on DSP

2014 ◽  
Vol 631-632 ◽  
pp. 806-810 ◽  
Author(s):  
Qing Xiang Hou ◽  
Xue Guang Yuan ◽  
Yan Gan Zhang ◽  
Jin Nan Zhang
Keyword(s):  
Control System ◽  
Digital Signal Processor ◽  
High Speed ◽  
Particle Swarm Optimization Algorithm ◽  
Low Frequency ◽  
Digital Signal ◽  
Rf Power ◽  
Swarm Optimization ◽  
Modified Particle Swarm Optimization ◽  
Stabilization Control

A polarization stabilization control system based on digital signal processor (DSP) is proposed in this paper. The system uses low frequency radio frequency (RF) power as control signal for polarization stabilization, and it does not need high-speed circuit to track fast polarization change. Modified particle swarm optimization algorithm is utilized and the effectiveness of polarization stabilization control is experimentally verified.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

Low Power, High Speed and Area Efficient Binary Count Multiplier

2016 ◽  
Vol 25 (04) ◽  
pp. 1650027 ◽  
Author(s):  
Kore Sagar Dattatraya ◽  
Belgudri Ritesh Appasaheb ◽  
Ramdas Bhanudas Khaladkar ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Digital Signal Processor ◽  
Word Length ◽  
High Speed ◽  
Digital Signal ◽  
General Purpose ◽  
Computation Method ◽  
Partial Product ◽  
Wallace Tree ◽  
Power Delay Product ◽  
Binary Count

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Design and Implementation of Audio Process System Based on DSP

2014 ◽  
Vol 945-949 ◽  
pp. 1752-1755
Author(s):  
Chui Xin Chen ◽  
Yang Hong Mao
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
High Speed ◽  
Audio Signal ◽  
Reference Value ◽  
Digital Signal ◽  
Real Time Processing ◽  
Audio Processing ◽  
Time Processing ◽  
Process System

The real-time processing for the input analog audio signal, audio processing program is proposed based on DSP. The system use FFT algorithm as the core, first, the input analog audio signal is sampled and A/D conversion using TLV320AIC23, and then use high speed digital signal processor to make real-time processing for the signal. Theoretical and experimental results show that the system can meet the design requirements, it has the advantage of high real-time and simple structure. The system has a good application and reference value for the development and design of data collecting and remote monitoring.

scholarly journals Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder

2019 ◽  
Vol 9 (1) ◽  
pp. 3028-3031
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Propagation Delay ◽  
Main Role ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Parallel Prefix

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

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