A distributed cellular approach of large scale SOM models for hardware implementation

Author(s):  
Laurent Rodriguez ◽  
Lyes Khacef ◽  
Benoit Miramond
2021 ◽  
Author(s):  
Jianming Cai ◽  
Han Bao ◽  
Quan Xu ◽  
Zhongyun Hua ◽  
Bocheng Bao

Abstract The Hindmarsh-Rose (HR) neuron model is built to describe the neuron electrical activities. Due to the polynomial nonlinearities, multipliers are required to implement the HR neuron model in analog. In order to avoid the multipliers, this brief presents a novel smooth nonlinear fitting scheme. We first construct two nonlinear fitting functions using the composite hyperbolic tangent functions and then implement an analog multiplierless circuit for the two-dimensional (2D) or three- dimensional (3D) HR neuron model. To exhibit the nonlinear fitting effects, numerical simulations and hardware experiments for the fitted HR neuron model are provided successively. The results show that the fitted HR neuron model with analog multiplierless circuit can display different operation patterns of resting, periodic spiking, and periodic/chaotic bursting, entirely behaving like the original HR neuron model. The analog multiplierless circuit has the advantage of low implementation cost and thereby it might be suitable for the hardware implementation of large-scale neural networks.


Author(s):  
DIANXUN SHUAI ◽  
XUE FANGLIANG

Data clustering has been widely used in many areas, such as data mining, statistics, machine learning and so on. A variety of clustering approaches have been proposed so far, but most of them are not qualified to quickly cluster a large-scale high-dimensional database. This paper is devoted to a novel data clustering approach based on a generalized particle model (GPM). The GPM transforms the data clustering process into a stochastic process over the configuration space on a GPM array. The proposed approach is characterized by the self-organizing clustering and many advantages in terms of the insensitivity to noise, quality robustness to clustered data, suitability for high-dimensional and massive data sets, learning ability, openness and easier hardware implementation with the VLSI systolic technology. The analysis and simulations have shown the effectiveness and good performance of the proposed GPM approach to data clustering.


2021 ◽  
Author(s):  
Dimitris Vordonis ◽  
Vassilis Paliouras

Detection for high-dimensional multiple-input multiple-output (MIMO) and massive MIMO (MMIMO) systems is an active field of research in wireless communications. While most works consider spatially uncorrelated channels, practical MMIMO channels are correlated. This paper investigates the impact of correlation on Sphere Decoder (SD), for both single-user (SU) and multi-user (MU) scenarios. The complexity of SD is mainly determined by the initial radius (IR) method and the number of visited nodes during detection. This paper employs an efficient IR and proposes a new metric constraint in the tree searching algorithm, that significantly decrease the number of visited nodes and render SD feasible for large-scale systems. In addition, an introduced hardware implementation featured with a one-node-per-cycle architecture, minimizes the latency of the detection process. Trade-offs between bit error rate (BER) performance and computational complexity are presented. The trade-offs are achieved by either modifying the backtracking mechanism or limiting the number of radius updates. Simulation results prove that the proposed optimizations are effective for both correlated and uncorrelated channels, regardless of the level of noise. The decoding gain of SD compared to the low-complexity linear detectors (LD) is higher in the presence of correlation than in the uncorrelated case. However, as expected, spatial correlation adversely affects the performance and the complexity of SD. Simulation results reported here also confirm that correlation at the side equipped with more antennas is less detrimental. Hardware implementation aspects are examined for both a Virtex-7 FPGA device and a 28-nm ASIC technology.<br>


2021 ◽  
Author(s):  
Dimitris Vordonis ◽  
Vassilis Paliouras

<div>Detection for high-dimensional multiple-input multiple-output (MIMO) and Massive MIMO (MMIMO) systems is an active field of research in wireless communications. While most works consider spatially uncorrelated channels, practical MMIMO channels are correlated. This paper investigates the impact of correlation on Sphere Decoder (SD), not only for Single-User (SU) but also for Multi-User (MU) scenarios. The complexity of SD is mainly determined by the Initial Radius (IR) method and the number of visited nodes during detection. This paper proposes both an efficient IR and a new metric constraint in the tree searching algorithm, that significantly decrease the number of visited nodes and render SD feasible for large-scale systems. In addition, a hardware implementation featured with a one-node-per-cycle architecture, minimizes the latency of the detection process. Trade-offs between bit error rate (BER) performance and computational complexity are presented, either modifying the backtracking mechanism or limiting the number of radius updates. Simulation results prove that the proposed optimizations are effective for both correlated and uncorrelated channels, regardless the level of noise. The decoding gain of SD compared to the low-complexity Linear Detectors (LD) is higher in the presence of correlation than in the uncorrelated case. However, as expected, spatial correlation adversely affects the performance and the complexity of SD. Simulation results reported here also confirm that correlation at the side equipped with more antennas is less detrimental. Hardware aspects are examined for both a Virtex-7 FPGA device and a 28-nm ASIC technology.</div>


2021 ◽  
Author(s):  
Ajay Singh ◽  
Vivek Saraswat ◽  
Maryam Shojaei Baghini ◽  
Udayan Ganguly

Abstract Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel physics based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of LSM reservoir using band-to-band-tunnelling (BTBT) based neuron. A low-power thresholding circuit and current-to-voltage converter design are proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. To verify the effect of the proposed neuron, a 36-neuron LSM reservoir is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area, 50x less area at a similar energy-per-spike, and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.


2013 ◽  
Vol 325-326 ◽  
pp. 1702-1705
Author(s):  
Xue Mei Li ◽  
Li Li

The EDA (Electronic Design Automation) technique which provides us an alternative method of circuit system based on the PC and information technology is a novel technique in modern electronic engineering field. Research on implementation of the DES (data encryption standard) has been paid much attention. In this paper, a description of the DES implementation on EDA box is presented in an alternative method which is suitable for EDA experimental teaching. The DES is set to different parts according to EDA experimental content. We introduce in detail the sub-circuits which consist of the circuits of the DES from simple units to large scale parts, which is easy for students or beginners to learn hardware implementation of cipher algorithm.


2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Punyashloka Debashis ◽  
Vaibhav Ostwal ◽  
Rafatul Faria ◽  
Supriyo Datta ◽  
Joerg Appenzeller ◽  
...  

Abstract Bayesian networks are powerful statistical models to understand causal relationships in real-world probabilistic problems such as diagnosis, forecasting, computer vision, etc. For systems that involve complex causal dependencies among many variables, the complexity of the associated Bayesian networks become computationally intractable. As a result, direct hardware implementation of these networks is one promising approach to reducing power consumption and execution time. However, the few hardware implementations of Bayesian networks presented in literature rely on deterministic CMOS devices that are not efficient in representing the stochastic variables in a Bayesian network that encode the probability of occurrence of the associated event. This work presents an experimental demonstration of a Bayesian network building block implemented with inherently stochastic spintronic devices based on the natural physics of nanomagnets. These devices are based on nanomagnets with perpendicular magnetic anisotropy, initialized to their hard axes by the spin orbit torque from a heavy metal under-layer utilizing the giant spin Hall effect, enabling stochastic behavior. We construct an electrically interconnected network of two stochastic devices and manipulate the correlations between their states by changing connection weights and biases. By mapping given conditional probability tables to the circuit hardware, we demonstrate that any two node Bayesian networks can be implemented by our stochastic network. We then present the stochastic simulation of an example case of a four node Bayesian network using our proposed device, with parameters taken from the experiment. We view this work as a first step towards the large scale hardware implementation of Bayesian networks.


2021 ◽  
Author(s):  
Dimitris Vordonis ◽  
Vassilis Paliouras

<div>Detection for high-dimensional multiple-input multiple-output (MIMO) and Massive MIMO (MMIMO) systems is an active field of research in wireless communications. While most works consider spatially uncorrelated channels, practical MMIMO channels are correlated. This paper investigates the impact of correlation on Sphere Decoder (SD), not only for Single-User (SU) but also for Multi-User (MU) scenarios. The complexity of SD is mainly determined by the Initial Radius (IR) method and the number of visited nodes during detection. This paper proposes both an efficient IR and a new metric constraint in the tree searching algorithm, that significantly decrease the number of visited nodes and render SD feasible for large-scale systems. In addition, a hardware implementation featured with a one-node-per-cycle architecture, minimizes the latency of the detection process. Trade-offs between bit error rate (BER) performance and computational complexity are presented, either modifying the backtracking mechanism or limiting the number of radius updates. Simulation results prove that the proposed optimizations are effective for both correlated and uncorrelated channels, regardless the level of noise. The decoding gain of SD compared to the low-complexity Linear Detectors (LD) is higher in the presence of correlation than in the uncorrelated case. However, as expected, spatial correlation adversely affects the performance and the complexity of SD. Simulation results reported here also confirm that correlation at the side equipped with more antennas is less detrimental. Hardware aspects are examined for both a Virtex-7 FPGA device and a 28-nm ASIC technology.</div>


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