scholarly journals Quantum Tunnelling based Ultra-compact and Energy Efficient Spiking Neuron enables Hardware Liquid State Machine

Author(s):  
Ajay Singh ◽  
Vivek Saraswat ◽  
Maryam Shojaei Baghini ◽  
Udayan Ganguly

Abstract Low-power and low-area neurons are essential for hardware implementation of large-scale SNNs. Various novel physics based leaky-integrate-and-fire (LIF) neuron architectures have been proposed with low power and area, but are not compatible with CMOS technology to enable brain scale implementation of SNN. In this paper, for the first time, we demonstrate hardware implementation of LSM reservoir using band-to-band-tunnelling (BTBT) based neuron. A low-power thresholding circuit and current-to-voltage converter design are proposed. We further propose a predistortion technique to linearize a nonlinear neuron without any area and power overhead. We establish the equivalence of the proposed neuron with the ideal LIF neuron to demonstrate its versatility. To verify the effect of the proposed neuron, a 36-neuron LSM reservoir is fabricated in GF-45nm PDSOI technology. We achieved 5000x lower energy-per-spike at a similar area, 50x less area at a similar energy-per-spike, and 10x lower standby power at a similar area and energy-per-spike. Such overall performance improvement enables brain scale computing.

Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.


2011 ◽  
Author(s):  
Βασίλειος Μαρδύρης

In last decades exponential reduction of integrated circuits feature size and increase in operating frequency was achieved in VLSI fabrication industry using the conventional CMOS technology. However the CMOS technology faces serious challenges as the CMOS transistor reaches its physical limits, such as ultra thin gate oxides, short channel effects, doping fluctuations and increased difficulty and consequently increased lithography cost in the nanometer scale. It is projected that the CMOS technology, in its present state will reach its limits when the transistors channel length reaches approximatly 7 nm, probably near 2019. Emerging technologies have been a topic of great interest in the last few years. The emerging technologies in nanoelectronics provide new computing possibilities that arise from their extremely reduced feature sizes. Quantum Cellular Automata (QCA) is one of the most promising emerging technologies in the fast growing area of nanoelectronics. QCA relies mostly on Coulombic interactions and uses innovative processing techniques which are very different from the CMOS-based model. QCAs are not only a new nanoelectronic model but also provide a new method of computation and information process. In QCA circuits computation and data transfer occurs simultaneously. Appling the QCA technology, the elementary building component (QCA cells) cover an area of a few nanometers. For this feature sizes the integration can reach values of 1012 cells/cm2 and the circuit switching frequency the THz level. The implementation of digital logic using QCA nanoelectronic circuits not only drives the already developed systems based on conventional technology to the nanoelectronic era but improves their performance significantly. At the present Ph.D. thesis, a study of QCA circuit clocking schemes is presented showing how these schemes contribute to the robustness of QCA circuits. A novel design of a QCA 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed for the first time. This methodology can be used to design 2n to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability.Furthermore in this Ph.D. thesis, a novel design of a small size, modular quantum-dot cellular automata (QCA) 2n to 1 multiplexer is proposed, These multiplexers can be used for memory addressing. The design objective is to develop an evolving modular design methodology which can produce QCA 2n to 1 multiplexer circuits, improved in terms of circuit area and operating frequency. In these implementations the circuit stability was a major issue and was considered carefully. In the recent years, Cellular Automata (CAs) have been widely used in order to model and simulate physical systems and also to solve scientific problems. CAs have also been successfully used as a VLSI architecture and proved to be very efficient in terms of silicon-area utilization and clock-speed maximization. In the present Ph.D. thesis a design methodology is developed for the first time, which can be used to design CA models using QCA circuitry. The implementation of CAs using QCA nanoelectronic circuits significantly improves their performance due to the unique properties of the nanoelectronic circuits. In this Ph.D. thesis a new CAD system we develope for the first time, and was named Design Automation Tool of 1-D Cellular Automata using Quantum Cellular Automata (DATICAQ), that builds a bridge between one-dimensional CAs as models of physical systems and processes and one-dimensional CAs as a nanoelectronic architecture. The CAD system inputs are the CA dimensionality, size, local rule, and the initial and boundary conditions imposed by the particular problem. DATICAQ produces as output the layout of the QCA implementation of the particular one-dimensional CA model. The proposed system also provides the simulation input vectors and their corresponding outputs, in order to simplify the simulation process. No prior knowledge of QCA circuit designing is required by the user. DATICAQ has been tested for a large number of QCA circuits. Paradigms of QCA circuits implementing CA models for zero and periodic boundary conditions are presented in the thesis. Simulations of CA models and the corresponding QCA circuits showed that the CA rules and models have been successfully implemented. At the present Ph.D. thesis, the design of large scale QCA circuits is analyzed and a study of the problems arising on complex algorithm implementation using QCAs is presented. One of the most important problems of the large scale QCA circuits is the synchronization of the internal signals of the circuit between the subsystems of the large QCA circuit. This problem becomes more difficult when the circuit includes signal loops. In the present thesis a methodology and a QCA circuit is presented for the first time, which solves the above mentioned synchronization problem. The QCA circuit implements the Firing Squad Synchronization Algorithm proposed by Mazoyer in order to solve the synchronization problem. The implementation was obtained using a one-dimensional 3-bit digital CA model. The QCA circuit is simulated and its operation is analyzed.


2020 ◽  
Vol 6 (18) ◽  
pp. eaaz6511 ◽  
Author(s):  
Gongjin Li ◽  
Zhe Ma ◽  
Chunyu You ◽  
Gaoshan Huang ◽  
Enming Song ◽  
...  

The sensing module that converts physical or chemical stimuli into electrical signals is the core of future smart electronics in the post-Moore era. Challenges lie in the realization and integration of different detecting functions on a single chip. We propose a new design of on-chip construction for low-power consumption sensor, which is based on the optoelectronic detection mechanism with external stimuli and compatible with CMOS technology. A combination of flipped silicon nanomembrane phototransistors and stimuli-responsive materials presents low-power consumption (CMOS level) and demonstrates great functional expansibility of sensing targets, e.g., hydrogen concentration and relative humidity. With a device-first, wafer-compatible process introduced for large-scale silicon flexible electronics, our work shows great potential in the development of flexible and integrated smart sensing systems for the realization of Internet of Things applications.


2016 ◽  
Vol 25 (09) ◽  
pp. 1650110 ◽  
Author(s):  
S. P. Valan Arasu ◽  
S. Baulkani

Medical image fusion is the process of deriving vital information from multimodality medical images. Some important applications of image fusion are medical imaging, remote control sensing, personal computer vision and robotics. For medical diagnosis, computerized tomography (CT) gives the best information about denser tissue with a lesser amount of distortion and magnetic resonance image (MRI) gives the better information on soft tissue with little higher distortion. The main scheme is to combine CT and MRI images for getting most significant information. The need is to focus on less power consumption and less occupational area in the implementations of the applications involving image fusion using discrete wavelet transform (DWT). To design the DWT processor with low power and area, a low power multiplier and shifter are incorporated in the hardware. This low power DWT improves the spatial resolution of fused image and also preserve the color appearance. Also, the adaptation of the lifting scheme in the 2D DWT process further improves the power reduction. In order to implement this 2D DWT processor in field-programmable gate array (FPGA) architecture as a very large scale integration (VLSI)-based design, the process is simulated with Xilinx 14.1 tools and also using MATLAB. When comparing the performance of this low power DWT and other available methods, this high performance processor has 24%, 54% and 53% of improvements on the parameters like standard deviation (SD), root mean square error (RMSE) and entropy. Thus, we are obtaining a low power, low area and good performance FPGA architecture suited for VLSI, for extracting the needed information from multimodality medical images with image fusion.


2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.


Author(s):  
Fadhilah Binti Noor Al Amin ◽  
Nabihah Ahmad ◽  
Siti Hawa Ruslan

<span>The rapid growth of the electronic system has become one of the challenges in the high performance of Very Large Scale Integration (VLSI) design and has contributed to the evolution of Phase Locked Loop (PLL) system design as one of the inevitable and significant necessities in the modern days. This design focus on the development of PLL system that can operate at a high performance within the Ultra-Wideband (UWB) frequency but consume low power that may be useful for future device implementation in the communication system. All proposed sub modules of PLL is highly suitable for low power and high speed application as each of them consumes overall power consumption around 2 µW until 1 mW with frequency from 3.1 GHz to 10.6 GHz. All the design architecture, schematic, simulation and analysis are implemented using Synopsys Tool in 90 nm CMOS technology. Through the overall analysis, it can be concluded that this proposed sub modules design of the PLL system has better performance compared to previous work in terms of power consumption and frequency.</span>


Author(s):  
Xiangyu Chen ◽  
Takeaki Yajima ◽  
Isao H. Inoue ◽  
Tetsuya Iizuka

Abstract Spiking neural networks (SNNs) inspired by biological neurons enable a more realistic mimicry of the human brain. To realize SNNs similar to large-scale biological networks, neuron circuits with high area efficiency are essential. In this paper, we propose a compact leaky integrate-and-fire (LIF) neuron circuit with a long and tunable time constant, which consists of a capacitor and two pseudo resistors (PRs). The prototype chip was fabricated with TSMC 65 nm CMOS technology, and it occupies a die area of 1392 m2. The fabricated LIF neuron has a power consumption of 6 W and a leak time constant of up to 1.2 ms (the resistance of PR is up to 600 MΩ). In addition, the time constants are tunable by changing the bias voltage of PRs. Overall, this proposed neuron circuit facilitates the very-large-scale integration (VLSI) of adaptive SNNs, which is crucial for the implementation of bio-scale brain-inspired computing.


2018 ◽  
Vol 27 (13) ◽  
pp. 1850205 ◽  
Author(s):  
Ramin Rajaei

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.


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