Carrier-based Pulse Width Modulation for Three-Level Inverters: Neutral Point Potential and Output Voltage Distortion

Author(s):  
Jang-hwan Kim ◽  
Seung-ki Sul
2021 ◽  
Author(s):  
Arifur Rahman Shohel

This project focuses on the topology of multilevel neutral point clamped (NPC)/H-bridge inverters and their modified modulation technique for high-power (megawatts) medium voltage (typically 6000 v) applications. A sinusodial pulse width in-phase disposition modulation is proposed for five-level NPC/H-bridge inverters. The inverter achieves good harmonic performance and low dv/dt in its output voltage waveforms in comparison to the conventional three-level NPC inverter. A seven-level NPC/H-bridge topology and its sinusodial pulse width in-phase disposition modulation are also proposed and investigated, which has better performance than the five-level inverters. Theoretical analysis and computer simulation are carried out for the proposed inverter topologies and algorithms. The output voltage waveforms and harmonic performance are verified by experiments on a five-level NPC/H-bridge inverters.


Energies ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 4328 ◽  
Author(s):  
Yunlei Zhang ◽  
Cungang Hu ◽  
Qunjing Wang ◽  
Yufei Zhou ◽  
Yue Sun

A selective harmonic elimination pulse width modulation (SHEPWM) control strategy is proposed to balance the neutral-point potential (NP) of a three-level active neutral-point-clamped (ANPC) converter. In this strategy, the chaotic ant colony algorithm (ACA) is adopted to solve the SHEPWM nonlinear equations, which does not require presetting the initial values of solutions and can get multiple solutions in the same modulation index. The influence of different solutions corresponding to the SHEPWM switching states on the NP is different, namely, some make the NP increase and others make the NP decrease. Therefore, the NP balancing can be effectively controlled by choosing appropriate solutions in different fundamental periods. The simulation and experimental results further verify the feasibility and effectiveness of the control strategy.


Author(s):  
Nhờ Văn NGUYỄN ◽  
HONG-PHONG NGUYEN LE

Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.


2017 ◽  
Vol 20 (2) ◽  
pp. 69
Author(s):  
Chen Yongchao ◽  
Li Yanda ◽  
Zhao Ling

For three-level inverter, complexity of control strategy and neutral-point potential imbalance problem of DC side is the bottleneck restricting its application. In order to solve the problem, a simplified implementation of three- level space vector pulse width modulation (SVPWM) considering neutral-point potential balancing is proposed in this paper. The proposed SVPWM algorithm is based on judging of three phase voltages and voltage-second balance principle, which does not need to perform the sine and cosine c alculations, and thus it is more convenient and effective than traditional SVPWM algorithm. Also, the neutral-point potential balancing can be realized conveniently and effectively. The proposed algorithm can not only effectively simplify the calculation and reduce calculation time greatly, but also achieve the same control effect as traditional SVPWM. It has certain reference significance and can be used to shorten sampling time and improve the inverter performance. Finally, the proposed SVPWM algorithm is verified by simulation and experimental results.


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