Multiscale modeling of defect-related phenomena in high-k based logic and memory devices

2017 ◽  
Author(s):  
Andrea Padovani ◽  
Luca Larcher ◽  
Francesco Maria Puglisi ◽  
Paolo Pavan
Keyword(s):  
Multiscale Modeling ◽  
Memory Devices ◽  
High K

Multiferroic Bi0.7Dy0.3FeO3 films as high k dielectric material for advanced non-volatile memory devices

2009 ◽  
Vol 45 (16) ◽  
pp. 821 ◽  
Author(s):  
K. Prashanthi ◽  
S.P. Duttagupta ◽  
R. Pinto ◽  
V.R. Palkar
Keyword(s):  
Dielectric Material ◽  
Memory Devices ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

Improved high-temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

2010 ◽  
Vol 87 (5-8) ◽  
pp. 1629-1633 ◽  
Author(s):  
J. Paul ◽  
V. Beyer ◽  
M. Czernohorsky ◽  
M.F. Beug ◽  
K. Biedermann ◽  
...  
Keyword(s):  
High Temperature ◽  
Memory Devices ◽  
Gate Stacks ◽  
Metal Gate ◽  
High K

Performance and Reliability of Si-Nanocrystal Double Layer Memory Devices with High-k Control Dielectrics

2009 ◽  
Author(s):  
G. Gay ◽  
G. Molas ◽  
M. Bocquet ◽  
E. Jalaguier ◽  
M. Gely ◽  
...  
Keyword(s):  
Double Layer ◽  
Memory Devices ◽  
High K ◽  
Si Nanocrystal

High-k dielectrics for future generation memory devices (Invited Paper)

2009 ◽  
Vol 86 (7-9) ◽  
pp. 1789-1795 ◽  
Author(s):  
J.A. Kittl ◽  
K. Opsomer ◽  
M. Popovici ◽  
N. Menou ◽  
B. Kaczer ◽  
...  
Keyword(s):  
Future Generation ◽  
Memory Devices ◽  
High K

Synthesis and Electrical Characterization of a MOS Memory Containing Pt Nanoparticles Deposited at a SiO2/ HfO2 Interface

2004 ◽  
Vol 830 ◽  
Author(s):  
Ch. Sargentis ◽  
K. Giannakopoulos ◽  
A. Travlos ◽  
D. Tsamakis
Keyword(s):  
High Frequency ◽  
Semiconductor Nanocrystals ◽  
Electrical Characterization ◽  
Pt Nanoparticles ◽  
Memory Device ◽  
Memory Devices ◽  
High K ◽  
High K Dielectric ◽  
Mos Device

ABSTRACTMOS memory devices containing semiconductor nanocrystals have drawn considerable attention recently, due to their advantages when compared to the conventional memories. Only little work has been done on memory devices containing metal nanoparticles.We describe the fabrication of a novel MOS device with embedded Pt nanoparticles in the HfO2 / SiO2 interface of a MOS device. Using as control oxide, a high-k dielectric, our device has a great degree of scalability. The fabricated nanoparticles are very small (about 5 nm) and have high density. High frequency C-V measurements demonstrate that this device operates as a memory device.

scholarly journals The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

2016 ◽  
Vol 30 (15) ◽  
pp. 1650279 ◽  
Author(s):  
Jinqiu Liu ◽  
Jianxin Lu ◽  
Jiang Yin ◽  
Bo Xu ◽  
Yidong Xia ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Rf Magnetron Sputtering ◽  
Memory Devices ◽  
Layer Deposition ◽  
High K ◽  
Charge Trapping Memory ◽  
Deposition Techniques ◽  
Composite Charge

The charge-trapping memory devices namely Pt/Al2O3/(Al2O[Formula: see text](Cu2O)[Formula: see text]/SiO2/[Formula: see text]-Si with 2, 3 and 4 nm SiO2 tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C–V curves of the memory devices with 2, 3 and 4 nm SiO2 tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al2O[Formula: see text](Cu2O)[Formula: see text] due to the different thicknesses of SiO2 tunneling layer.

Electrical Characteristics of Memory Devices With a High-$k$$\hbox{HfO}_{2}$ Trapping Layer and Dual $\hbox{SiO}_{2}/\hbox{Si}_{3}\hbox{N}_{4}$ Tunneling Layer

2007 ◽  
Vol 54 (10) ◽  
pp. 2699-2705 ◽  
Author(s):  
Ying Qian Wang ◽  
Wan Sik Hwang ◽  
Gang Zhang ◽  
G. Samudra ◽  
Yee-Chia Yeo ◽  
...  
Keyword(s):  
Memory Devices ◽  
Electrical Characteristics ◽  
High K

Low voltage operation of non-volatile flexible OFET memory devices using high- k P(VDF-TrFE) gate dielectric and polyimide charge storage layer

2016 ◽  
Vol 108 ◽  
pp. 39-46 ◽  
Author(s):  
Mao-Shen Lu ◽  
Hung-Chin Wu ◽  
Yu-Wei Lin ◽  
Mitsuru Ueda ◽  
Wen-Chang Chen
Keyword(s):  
Gate Dielectric ◽  
Low Voltage ◽  
Charge Storage ◽  
Memory Devices ◽  
Low Voltage Operation ◽  
High K
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