Comparing Variation-tolerance and SEU/TID-Resilience of Three SRAM Cells in 28nm FD-SOI Technology: 6T, Quatro, and we-Quatro

2020 ◽  
Author(s):  
Le Dinh Trang Dang ◽  
Trinh Dinh Linh ◽  
Ngyuen Thanh Dat ◽  
Changhong Min ◽  
Jinsang Kim ◽  
...  
Keyword(s):  
Variation Tolerance ◽  
Soi Technology

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures

2011 ◽  
Vol E94-A (12) ◽  
pp. 2669-2675 ◽  
Author(s):  
Chikara HAMANAKA ◽  
Ryosuke YAMAMOTO ◽  
Jun FURUTA ◽  
Kanto KUBOTA ◽  
Kazutoshi KOBAYASHI ◽  
...  
Keyword(s):  
Shift Register ◽  
Flip Flop ◽  
Variation Tolerance ◽  
Modular Redundancy

Sigma-Delta ADC on SOI Technology for Working at High Temperatures

2020 ◽  
Vol 63 (11) ◽  
pp. 586-595
Author(s):  
Alexander Korotkov ◽  
Dmitry Morozov ◽  
Mikhail Pilipko ◽  
Mikhail Yenuchenko
Keyword(s):  
High Temperatures ◽  
Sigma Delta ◽  
Sigma Delta Adc ◽  
Soi Technology

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

2008 ◽  
Vol 39 (9) ◽  
pp. 1130-1139 ◽  
Author(s):  
Gilles Jacquemod ◽  
Lionel Geynet ◽  
Benjamin Nicolle ◽  
Emeric de Foucauld ◽  
William Tatinian ◽  
...  
Keyword(s):  
Soi Technology
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