Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

1998 ◽  
Author(s):  
H. Lorenz ◽  
C. Engel
Keyword(s):  
Focused Ion Beam ◽  
Cell Function ◽  
Dielectric Breakdown ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Floating Gate ◽  
Leakage Path ◽  
Contrast Technique ◽  
Voltage Contrast

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

Carbon Coating for Electron Beam Testing and Focus Ion Beam Reconfiguration

1996 ◽  
Author(s):  
P. Perdu ◽  
G. Perez ◽  
M. Dupire ◽  
B. Benteo
Keyword(s):  
Electron Beam ◽  
Sample Preparation ◽  
Carbon Coating ◽  
Focused Ion Beam ◽  
Sacrificial Layer ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Fault Analysis ◽  
Voltage Contrast ◽  
The Right

Abstract To debug ASIC we likely use accurate tools such as an electron beam tester (Ebeam tester) and a Focused Ion Beam (FIB). Interactions between ions or electrons and the target device build charge up on its upper glassivation layer. This charge up could trigger several problems. With Ebeam testing, it sharply decreases voltage contrast during Image Fault Analysis and hide static voltage contrast. During ASIC reconfiguration with FIB, it could induce damages in the glassivation layer. Sample preparation is getting a key issue and we show how we can deal with it by optimizing carbon coating of the devices. Coating is done by an evaporator. For focused ion beam reconfiguration, we need a very thick coating. Otherwise the coating could be sputtered away due to imaging. This coating is use either to avoid charge-up on glassivated devices or as a sacrificial layer to avoid short circuits on unglassivated devices. For electron beam Testing, we need a very thin coating, we are now using an electrical characterization method with an insitu control system to obtain the right thin thickness. Carbon coating is a very cheap and useful method for sample preparation. It needs to be tuned according to the tool used.

Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs

2000 ◽  
Author(s):  
T. Kane ◽  
M. Cambra ◽  
M. Tenney ◽  
P. McGinnis ◽  
A. Domenicucci ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Scanning Capacitance Microscopy ◽  
Isolation Techniques ◽  
Silicon On Insulator Technology ◽  
Soi Technology

Abstract This paper discusses the challenges involved in testing microprocessors incorporating silicon-on-insulator (SOI) technology and assesses new characterizations tools, such as scanning capacitance microscopy (SCM), focused ion beam (FIB) analysis, and AFM electrical probing, that show promise when used to examine SOI device anomalies and failure modes.

Failure Analysis Using Voltage Contrast and Ebic

1998 ◽  
Vol 523 ◽  
Author(s):  
Larry Rice ◽  
Wei Chen
Keyword(s):  
Electron Microscopy ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Sem Analysis ◽  
Silicon On Insulator ◽  
Traditional Use ◽  
Critical Dimensions ◽  
Voltage Contrast ◽  
Microscopy Techniques

AbstractAs ULSI device critical dimensions continue to shrink to submicron sizes, electron microscopy techniques such as electron beam induced current (EBIC) and voltage contrast are finding more applications towards pinpointing failure sites for subsequent cross sectioning or deprocessing. In addition to the traditional use of EBIC for junction delineation, EBIC has been applied to locate leakage sites in capacitor structures and silicon-on-insulator (SOI) devices as well. Similarly, voltage contrast has been applied to identify single or multiple opens in via chains which consist of thousands of vias. In addition to a brief revisit of the basic principles of EBIC and voltage contrast, focus will be placed on the application of EBIC and voltage contrast in failure analysis of semiconductor devices. Examples of using voltage contrast combined with precision cross section focused ion beam (XFIB) for identifying the failure mechanism of 0.8μm vias will be presented. Also, the use of EBIC for identifying leakage sites in SOI and bipolar devices and subsequent FIB/scanning electron microscopy (SEM) analysis will be presented.

The Joy of SOI: As Viewed from a Backside FIB Perspective

2005 ◽  
Author(s):  
Steven Herschbein ◽  
Chad Rue ◽  
Carmelo Scrudato
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Surface Preparation ◽  
High Volume ◽  
Silicon On Insulator ◽  
Structure Alignment ◽  
Instruction Set ◽  
Post Process ◽  
Voltage Contrast ◽  
Global And Local

Abstract For most advanced semiconductor products, the preferred methodology for achieving Focused Ion Beam (FIB) circuit modification and node access is through the backside of the chip. The high density of interconnect wiring and the presence of C4 solder bumping has made complex edits virtually impossible with conventional frontside techniques. IBM has developed a set of procedures for performing backside edit on circuits built using the Silicon-On-Insulator (SOI) process. While the basic approach and techniques parallel many of the established practices developed for handling transistors built in conventional bulk silicon, there are a number of key and critical differences. In this paper, we will address the basic instruction set developed for successful FIB work on SOI product. This will include backside silicon surface preparation, charge control, endpointing during high volume silicon removal, global and local coordinate lock techniques, floor voltage contrast phenomena, floor preparation and preservation, fill pattern issues and advantages, and finally the target structure alignment, access, connection and/or removal. Post process bake and handling will also be discussed.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Analysis of Voltage Contrast in Secondary Electron Images Using a High-Energy Electron Spectrometer

2019 ◽  
Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Sample Surface ◽  
High Energy ◽  
Secondary Electrons ◽  
Analysis Technique ◽  
Quantitative Understanding ◽  
Voltage Contrast ◽  
Acceleration Voltage ◽  
Failure Localization

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

Site-Specific Low Angle Plasma FIB Milling for Cross-Sectional Electrical Characterization

2019 ◽  
Author(s):  
Chuan Zhang ◽  
Jane Y. Li ◽  
John Aguada ◽  
Howard Marks
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Electrical Characteristic ◽  
Preparation Method ◽  
Ion Beam ◽  
Grazing Angle ◽  
Electrical Characterization ◽  
Sample Preparation Method ◽  
Cross Sectional ◽  
Site Specific

Abstract This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.

Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis

2016 ◽  
Author(s):  
Dirk Doyle ◽  
Lawrence Benedict ◽  
Fritz Christian Awitan
Keyword(s):  
Cross Section ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Gate Oxide ◽  
Top Down ◽  
New Techniques ◽  
First Case ◽  
Transmission Electron ◽  
Scanning Transmission

Abstract Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

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