Electron Beam Absorbed Current as a Means of Locating Metal Defectivity on 45nm SOI Technology

2010 ◽  
Author(s):  
K. Dickson ◽  
G. Lange ◽  
K. Erington ◽  
J. Ybarra
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Back Side ◽  
Soi Technology

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the back side of the device as a means of locating metallization defects on flip chip 45nm SOI technology.

Advanced Backside Defect Isolation Techniques Using Electron Beam Absorbed Current to Locate Metal Defectivity on Bulk and SOI Technology

2011 ◽  
Author(s):  
K. Erington ◽  
K. Dickson ◽  
G. Lange ◽  
J. Z. Garcia ◽  
J. Ybarra ◽  
...  
Keyword(s):  
Electron Beam ◽  
Sample Preparation ◽  
Flip Chip ◽  
State Of The Art ◽  
Bulk Silicon ◽  
Silicon Technology ◽  
Isolation Techniques ◽  
Defect Isolation ◽  
Soi Technology ◽  
Preparation Equipment

Abstract This paper describes the use of Electron Beam Absorbed Current (EBAC) mapping performed from the backside of the device as a means of locating metallization defects on state of the art bulk silicon and SOI based microprocessor technologies. It builds on previous work which focused only on flip-chip SOI samples. This paper will demonstrate additional EBAC techniques and the ability to analyze devices processed in bulk silicon technology. Also included are the results obtained from an SOI device mounted in a non flipchip package type. Additional details related to sample preparation, equipment used, and improved practices are described.

Evaluation of Low Stress Photo-Sensitive Spin On Dielectric Layers for Through Silicon Via (TSV) Copper Redistribution Layers

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000666-000698
Author(s):  
Christopher Jahnes ◽  
Eric Huenger ◽  
Scott Kisting
Keyword(s):  
Power Distribution ◽  
Flip Chip ◽  
Dielectric Materials ◽  
Back Side ◽  
Thermal Reliability ◽  
Dielectric Layers ◽  
Chip Size ◽  
Package Density ◽  
Silicon Vias ◽  
Wafer Thinning

To increase performance of semiconductor devices advances in packaging such as chip stacking (3D) and silicon carrier technologies (SoC) are being developed. Adaptation of these packaging fabrication methods offers the ability to incorporate functionality as well as provide memory and power distribution on one IC with increased signal bandwidth. An enabling element in both the stacking and silicon carrier technologies is through silicon vias (TSV) which electrically connect dies to a silicon carrier or via stacked chips (1). Creation of TSV involves via fabrication, wafer thinning and back side wafer finishing, to name a few, some of which are relatively new to semiconductor processing. Furthermore, because the wafer backside is accessible it can now be utilized to route wiring to further increase package density. The focus of this research was to evaluate photo-sensitive spin on dielectric materials (SOD) that can be used as the backside wiring levels, commonly referred to as redistribution layers (RDL) in TSV technologies. The two materials evaluated are; the epoxy based Dow INTERVIA™ 8023 Dielectric and the Benzocyclobutene (BCB) polymer, Dow CYCLOTENE™ 4000 product series. These dielectric materials have low stress and provide good planarization (2). Test vehicles with a chip size of 3.7 cm x 2.26 cm were fabricated with a 6 um wide copper RDL layer using the SOD materials of interest as well as conventional PECVD SiO2/SiN dielectric layers. The large chip size accommodated parallel Cu lines running 1.8 cm long with a spacing of 3 m and represented an aggressive shorting test for the SOD materials. It also enhances chip distortion after thinning and is evaluated for all three test vehicles. Chips were then electrically tested through simulated 260° C reflow cycles (for flip chip joining) and accelerated thermal reliability tests from −55° C to 125° C for 1000 cycles.

Development of 3D System-in-Package with TSV Technology

2014 ◽  
Vol 2014 (1) ◽  
pp. 000612-000617 ◽  
Author(s):  
Shota Miki ◽  
Takaharu Yamano ◽  
Sumihiro Ichikawa ◽  
Masaki Sanada ◽  
Masato Tanaka
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Organic Substrate ◽  
Back Side ◽  
Final Thickness ◽  
Chip Technology ◽  
Type Semiconductor ◽  
Interconnect Reliability ◽  
Solder Balls ◽  
Carrier Wafer

In recent years, products such as smart phones, tablets, and wearable devices, are becoming miniaturized and high performance. 3D-type semiconductor structures are advancing as the demand for high-density assembly increases. We studied a fabrication process using a SoC die and a memory die for 3D-SiP (System in Package) with TSV technology. Our fabrication is comprised of two processes. One is called MEOL (Middle End of Line) for exposing and completing the TSV's in the SoC die, and the other is assembling the SoC and memory dice in a 3D stack. The TSV completion in MEOL was achieved by SoC wafer back-side processing. Because its final thickness will be a thin 50μm (typical), the SoC wafer (300 mm diameter) is temporarily attached face-down onto a carrier-wafer. Careful back-side grinding reveals the “blind vias” and fully opens them into TSV's. A passivation layer is then grown on the back of the wafer. With planarization techniques, the via metal is accessed and TSV pads are built by electro-less plating without photolithography. After the carrier-wafer is de-bonded, the thin wafer is sawed into dice. For assembling the 3D die stack, flip-chip technology by thermo-compression bonding was the method chosen. First, the SoC die with copper pillar bumps is assembled to the conventional organic substrate. Next the micro-bumps on the memory die are bonded to the TSV pads of the SoC die. Finally, the finished assembly is encapsulated and solder balls (BGA) are attached. The 3D-SiP has passed both package-level reliability and board-level reliability testing. These results show we achieved fabricating a 3D-SiP with high interconnect reliability.

Development of Organic Multi Chip Package for High Performance Application

2013 ◽  
Vol 2013 (1) ◽  
pp. 000414-000414 ◽  
Author(s):  
Noriyoshi Shimizu ◽  
Wataru Kaneda ◽  
Hiromu Arisaka ◽  
Naoyuki Koizumi ◽  
Satoshi Sunohara ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Metal Layer ◽  
Small Diameter ◽  
Organic Substrate ◽  
Back Side ◽  
Test Results ◽  
Manufacturing Method ◽  
Separate Step ◽  
High Performance Application

In recent years, it has become apparent that the conventional FC-BGA (Flip Chip Ball Grid Array) substrate manufacturing method (Electroless Cu plating, Desmear, Laser Drilling processing) is reaching its limits for finer wiring dimensions and narrower pitches of the flip chip pad. On the other hand, the demand for miniaturization and higher density continues to increase. Our solution is the Organic Multi Chip Package, a combined organic interposer and organic substrate. Unlike a conventional 2.5D interposer that is separately manufactured and then attached to a substrate PWB (Printed Wire Board), the interposer of our Organic Multi Chip Package is built directly onto an organic substrate. First normal build-up layers are laminated on both sides of the PWB core and metal traces formed by conventional semi-additive techniques. After the back side is coated with a typical SR layer for FC-BGA, the top surface and its laser-drilled vias are smoothed by CMP (Chemical Mechanical Polishing). A thin-film process is used to deposit the interposer's insulating resin layers. Then normal processes are applied to open small diameter vias and a metal seed layer is sputtered on. The wiring is patterned, and the metal traces are fully formed by plating. Finally, the Cu pads on the top layer are treated by OSP (Organic Solderability Preservative). In this paper we discuss results using a prototype 40 mm × 40 mm Organic Multi Chip Package. The prototype's organic substrate has a two-metal layer core with 100 μm diameter through-holes, two build-up layers on the chip side, and three plus a solder resist layer on the BGA side. The interposer has four wiring layers. Thus the structure of the prototype is 4+(2/2/3). For evaluation purposes, there are four patterns of lines and spaces on the interposer: 2 μm/2 μm, 3 μm/3 μm, 4 μm/4 μm, and 5 μm/5 μm. The metal trace thicknesses are 2.5 μm, via diameters are 10 μm, pad pitches are 40 μm, and the Cu pad diameters are 25 μm. These dimensions allow the Organic Multi Chip Package to easily make the pitch conversions of the IC to the PCB. With a 4+(2/2/3) structure, the Organic Multi Chip Package is asymmetric, raising concerns about package warping. However, the warping can be reduced by the optimization of structure and materials. In this way, we were able to connect a high pin-count logic chip to standard Wide I/O memory chips. We think that there are at least two obvious advantages of the Organic Multi Chip Package. The first is a total height reduction compared to a structure with a separate silicon interposer attached to a PWB substrate. The Organic Multi Chip Package, with its built-on interposer, eliminates the need for solder joints between the interposer and substrate. In addition, the fine resin layers make our interposer much thinner than a silicon interposer. The second advantage is simpler assembly. Our structure does not require the separate step of assembling an interposer to the substrate. Assembly costs should be lower and yields higher. In this paper we demonstrate the successful attainment of fine lines and spaces on the Organic Multi Chip Package. We also show and discuss reliability test results.

FUNDAMENTALS OF THE SQUEEZE-FLOW BETWEEN A HEAT SINK AND A FLIP-CHIP

2008 ◽  
Vol 32 (3-4) ◽  
pp. 467-486 ◽  
Author(s):  
M.A. Marois ◽  
M. Lacroix
Keyword(s):  
Heat Sink ◽  
Flip Chip ◽  
String Model ◽  
Thermal Interface Material ◽  
Squeeze Flow ◽  
Back Side ◽  
Two Dimensional ◽  
Particle Volume ◽  
Volume Fractions ◽  
Drop Flow

The paper presents the fundamentals of the squeeze-flow of the thermal interface material (TIM) that takes place during the pressing of a heat sink to the back side of a flip-chip is studied. A two-dimensional string model is developed for predicting the time-varying plate separation and squeeze-rate in terms of the squeeze force. The predictions are compared to a one-dimensional string model and to a squeeze-drop flow model. Results indicate that the flow resulting from the squeezing of a string of TIM between two rigid plates is truly two-dimensional. The effect of surface tension and of the heat transfer is found to be negligible under the assembly conditions. The flow behaviour of the TIM with suspensions of high thermal conductivity particles is also investigated. It is shown that the fluid remains Newtonian for particle volume fractions smaller than 30%. For volume fractions larger than 30%, the fluid becomes Non-Newtonian during the early stages of the squeezing process, i.e. for t ≤ 1s. In the later stages however (t > 10s), the fluid may be considered Newtonian.

scholarly journals Back Side Illumination Image Sensor Characterization by Backside Circuit Editing

2021 ◽  
Author(s):  
Jian Yu ◽  
Jin Xu ◽  
Niel Sanico
Keyword(s):  
Electron Beam ◽  
Optical Imaging ◽  
Ion Beam ◽  
Image Sensor ◽  
Back Side ◽  
Novel Approach ◽  
Side Illumination

Abstract The characterization of Back Side Illumination (BSI) Image Sensor is challenging because of its unique construct with silicon on top. A novel approach for the BSI Image sensor characterization will be presented in this paper. The proposed approach utilizes the circuit editing through the silicon (backside) by ion beam and optical imaging. This technique allows access to the buried conductors and creates probe points for measurements, which are typically performed by an optical prober, electron beam prober or a mechanical micro/nano prober.

Localizing IC Defect Using Nanoprobing: A 3D Approach

2019 ◽  
Author(s):  
Jane Y. Li ◽  
Chuan Zhang ◽  
John Aguada ◽  
Christopher Nemirow ◽  
Howard Marks
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Multiple Perspectives ◽  
Site Specific ◽  
Root Cause ◽  
Area Of Interest ◽  
Defect Localization ◽  
Cmos Ic

Abstract This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.

FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

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