High-speed DACs with random multiple data-weighted averaging algorithm

2003 ◽  
Author(s):  
Yu-Hong Lin ◽  
Da-Huei Lee ◽  
Cheng-Chung Yang ◽  
Tai-Haur Kuo
Keyword(s):  
High Speed ◽  
Weighted Averaging ◽  
Multiple Data ◽  
Data Weighted Averaging

SFDR Improvement Algorithms for Current-Steering DACs

2015 ◽  
Vol 643 ◽  
pp. 101-108 ◽  
Author(s):  
Shaiful Nizam Mohyar ◽  
Masahiro Murakami ◽  
Atsushi Motozawa ◽  
Haruo Kobayashi ◽  
Osamu Kobayashi ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Weighted Averaging ◽  
Current Steering ◽  
Switching Sequence ◽  
Digital To Analog Converters ◽  
Compensation Methods ◽  
Spurious Free Dynamic Range ◽  
Data Weighted Averaging ◽  
Combined Algorithm

This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

A Framework of RFID-Based Complex Event Processing System for Assembly Manufacturing

2015 ◽  
Vol 751 ◽  
pp. 287-292 ◽  
Author(s):  
Na Mao ◽  
Jie Tan
Keyword(s):  
High Speed ◽  
Uncertain Data ◽  
Processing System ◽  
Business Environment ◽  
Complex Event Processing ◽  
Event Processing ◽  
Manufacturing Companies ◽  
Multiple Data ◽  
High Speed Trains ◽  
Manufacturing Applications

Owing to the dynamic and competitive business environment, manufacturing companies take real-time monitoring and rapid decision making based on RFID applications, which brings huge volume of information and events generated in the defined manufacturing workflows. Complex Event Processing (CEP) is introduced to solve the problems mentioned above. CEP is applied to handle diverse and large amount of low-level multiple data and primitive events for the purpose of identifying meaningful event patterns. It is very important to integrate the CEP technology to the manufacturing workflows. In this paper, we provide a novel framework of RFID-based complex event processing system for assembly manufacturing applications like cars and high-speed trains. It bridges the hardware in workshops and enterprise applications. The Complex Event Management System (CEMS), which is the kernel of the framework, can filter the irrelevant events and work with uncertain data. Furthermore, a concrete example is used to describe the framework and validate the feasibility in assembly monitoring of the car manufacturing.

scholarly journals Second order noise shaping for data-weighted averaging technique to improve sigma-delta DAC performance

2021 ◽  
Vol 10 (1) ◽  
pp. 79
Author(s):  
Ali Kerem Nahar ◽  
Ansam Subhi Jaddar ◽  
Hussain K. Khleaf ◽  
Mohmmed Jawad Mortada Mobarek
Keyword(s):  
Power Dissipation ◽  
Second Order ◽  
Weighted Averaging ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Averaging Technique ◽  
Delta Sigma ◽  
Low Levels ◽  
Digital To Analog ◽  
Data Weighted Averaging

<p>In general, the noise shaping responses, a cyclic second order response is delivered by the method of data weighted averaging (DWA) in which the output of the digital-to-analog convertor (DAC) is restricted to one of two states. DWA works efficiently for rather low levels of quantizing; it begins presenting considerable difficulties when internal levels of quantizing are extended further. Though, each added bit of internal quantizing causes an exponentially increasing in power dissipation, complexity and size of the DWA logic and the DAC. This gives a controlled seconnd order response accounting for the mismatch of the elements of DAC. The multi-bit DAC is made up of numerous single-bit DACs having values thereof chosen via a digital encoder. This research presents a discussion of the influence of mismatching between unit elements of the Delta-Sigma DAC. This results in a constrained second order response accounting for mismatch of DAC elements. The results of the simulation showed how the effectiveness of DWA method is in reducing band tones. Furthermore, DWA method has proved its efficiency in solving the mismatching of DAC unit elements. The noise of the mismatching elements is enhanced 11 dB at 0.01 with the proposed DWA, thereby enhancing the efficiency of the DAC in comparison to the efficiency of the DAC with no use of the circuit of DWA</p>

scholarly journals Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

2019 ◽  
Vol 37 (3) ◽  
pp. 515-522
Author(s):  
Tianjiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Fpga Implementation ◽  
Maximum Frequency ◽  
Ldpc Decoder ◽  
Memory Strategies ◽  
Multiple Data ◽  
Decoder Architecture ◽  
Place And Route ◽  
Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging

2020 ◽  
Vol 105 ◽  
pp. 104905
Author(s):  
Qihui Zhang ◽  
Jing Li ◽  
Ning Ning ◽  
Qi Yu ◽  
Kejun Wu ◽  
...  
Keyword(s):  
Second Order ◽  
Sar Adc ◽  
Weighted Averaging ◽  
Noise Shaping ◽  
Error Feedback ◽  
Feedback Structure ◽  
Data Weighted Averaging
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