SFDR Improvement Algorithms for Current-Steering DACs

2015 ◽  
Vol 643 ◽  
pp. 101-108 ◽  
Author(s):  
Shaiful Nizam Mohyar ◽  
Masahiro Murakami ◽  
Atsushi Motozawa ◽  
Haruo Kobayashi ◽  
Osamu Kobayashi ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Weighted Averaging ◽  
Current Steering ◽  
Switching Sequence ◽  
Digital To Analog Converters ◽  
Compensation Methods ◽  
Spurious Free Dynamic Range ◽  
Data Weighted Averaging ◽  
Combined Algorithm

This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450053 ◽  
Author(s):  
FAN XIA ◽  
YIQIANG ZHAO ◽  
GONGYUAN ZHAO
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Differential Nonlinearity ◽  
Spurious Free Dynamic Range ◽  
Source Block ◽  
Current Steering Dac

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

An Improved Data Weighted Averaging for Segmented Current-Steering DACs

2013 ◽  
Vol 748 ◽  
pp. 868-873
Author(s):  
Dan Zheng ◽  
Wei Ni ◽  
Rui Zhang ◽  
Yong Sheng Yin
Keyword(s):  
Dynamic Performance ◽  
Weighted Averaging ◽  
Current Steering ◽  
Output Impedance ◽  
Digital To Analog Converters ◽  
Starting Position ◽  
High Level ◽  
Data Weighted Averaging ◽  
Element Sequence ◽  
Device Size

An improved DWA method for 14-bit 5+4+5 segmented current-steering digital-to-analog converters is proposed. Through to SFDR and dynamic performance of compromise consideration, this method uses two barrel shifters to control the starting position of the current element sequence every four clocks. Compared with the conventional DWA method, it features smaller device size and improves SFDR. And based on SIMULINK platform, through the establishment of high level of current steering D/A converter model with matching errors and output impedance. The simulation results show that SFDR is improved about 25dB.

A 12-Bit 500-MS/s Current Steering CMOS DAC for High-Speed PLC Modems

2016 ◽  
Vol 25 (10) ◽  
pp. 1650122 ◽  
Author(s):  
Chan-Keun Kwon ◽  
Junil Moon ◽  
Soo-Won Kim
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Design Procedure ◽  
Weighted Averaging ◽  
Total Power ◽  
Cmos Process ◽  
Current Steering ◽  
Current Cell ◽  
Total Power Consumption

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-[Formula: see text]m CMOS process with an active area of 2.445[Formula: see text]mm2, which achieves a differential non linearity (DNL) of 0.25[Formula: see text]LSB and an integral non-linearity (INL) of 0.19[Formula: see text]LSB. Additionally, the SFDR increases by 13.2[Formula: see text]dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176[Formula: see text]mW from a 1.8-V supply voltage.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

Mitigating the Effects of Non-Linear Distortion Using Polarizers in Microwave Photonic Link

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Sarika Singh ◽  
Sandeep K. Arya ◽  
Shelly Singla
Keyword(s):  
Dynamic Range ◽  
Extinction Ratio ◽  
Polarization Angle ◽  
Third Order ◽  
Microwave Photonic ◽  
Linear Behavior ◽  
Spurious Free Dynamic Range ◽  
Non Linear ◽  
Intermodulation Distortions ◽  
Insertion Losses

AbstractA scheme to suppress nonlinear intermodulation distortion in microwave photonic (MWP) link is proposed by using polarizers to compensate inherent non-linear behavior of dual-electrode Mach-Zehnder modulator (DE-MZM). Insertion losses and extinction ratio have also been considered. Simulation results depict that spurious free dynamic range (SFDR) of proposed link reaches to 130.743 dB.Hz2/3. A suppression of 41 dB in third order intermodulation distortions and an improvement of 15.3 dB is reported when compared with the conventional link. In addition, an electrical spectrum at different polarization angles is extracted and 79^\circ is found to be optimum value of polarization angle.

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