Hardware Implementation of AES Algorithm with Logic S-box

2017 ◽  
Vol 26 (09) ◽  
pp. 1750141 ◽  
Author(s):  
Soufiane Oukili ◽  
Seddik Bri
Keyword(s):  
Data Security ◽  
High Speed ◽  
Hardware Implementation ◽  
Network Applications ◽  
Aes Algorithm ◽  
Communication Techniques ◽  
High Speed Network ◽  
Cryptographic Algorithm ◽  
Hardware Implementations ◽  
Field Programmable

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

scholarly journals A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam
Keyword(s):  
Data Security ◽  
High Speed ◽  
Fpga Implementation ◽  
Digital Data ◽  
Low Area ◽  
Aes Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Cyber Crimes ◽  
The Look

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

scholarly journals FPGA Based OTP Generation System for Data Security

2020 ◽  
Vol 8 (5) ◽  
pp. 1836-1839
Keyword(s):  
Conventional Method ◽  
Data Security ◽  
Hash Function ◽  
The Internet ◽  
Generation System ◽  
Replay Attack ◽  
Aes Algorithm ◽  
Cipher Text ◽  
Cryptographic Algorithm ◽  
One Time Password

The password system is the most conventional method among validation techniques on the internet and is operated more easily and effectively than other methods. However, it is a vulnerable method against attacks such as eavesdropping or replay attack. To prevail over this problem, OTP (One Time Password) technique is used. The most popular OTP is HOTP algorithm, which is based on one-way hash function SHA-1. The recent researches show the weakness of the hash function. So, in this paper we created a module which uses another cryptographic algorithm. Cryptography in the current world serves an important role in data security. Cryptography means writing of secret codes (cipher text) which is in an unintelligible form and cannot be read unless we have a perfect key to decode it. The proposed method is AES algorithm (128 bit) followed by Middle Square method to generate an OTP. As OTP is a 4-6 bit number we will decrease the AES output to a 4-6 bit through Middle Square method and this OTP can be used as a security tool in many cases like online transaction purposes.

scholarly journals Optimization and Implementation of Synthetic Basis Feature Descriptor on FPGA

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 391
Author(s):  
Dah-Jye Lee ◽  
Samuel G. Fuller ◽  
Alexander S. McCown
Keyword(s):  
High Speed ◽  
Feature Detection ◽  
Hardware Implementation ◽  
Feature Matching ◽  
Image Features ◽  
Image Feature ◽  
Superior Performance ◽  
Feature Descriptor ◽  
Binary Descriptors ◽  
Field Programmable

Feature detection, description, and matching are crucial steps for many computer vision algorithms. These steps rely on feature descriptors to match image features across sets of images. Previous work has shown that our SYnthetic BAsis (SYBA) feature descriptor can offer superior performance to other binary descriptors. This paper focused on various optimizations and hardware implementation of the newer and optimized version. The hardware implementation on a field-programmable gate array (FPGA) is a high-throughput low-latency solution which is critical for applications such as high-speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. We compared our solution to other hardware designs of binary descriptors. We demonstrated that our implementation of SYBA as a feature descriptor in hardware offered superior image feature matching performance and used fewer resources than most binary feature descriptor implementations.

High speed network applications and implications for fiberoptic and copper connections

2000 ◽  
Author(s):  
Dean Collins ◽  
John Antonishek ◽  
Sean Sell ◽  
Alan Mink
Keyword(s):  
High Speed ◽  
Network Applications ◽  
High Speed Network

scholarly journals Impact of Modern Virtualization Methods on Timing Precision and Performance of High-Speed Applications

2019 ◽  
Vol 11 (8) ◽  
pp. 179 ◽  
Author(s):  
Veronika Kirova ◽  
Kirill Karpov ◽  
Eduard Siemens ◽  
Irina Zander ◽  
Oksana Vasylenko ◽  
...  
Keyword(s):  
Virtual Environments ◽  
Virtual Environment ◽  
High Speed ◽  
High Performance ◽  
Estimation Accuracy ◽  
Network Applications ◽  
High Speed Network ◽  
Timing Precision ◽  
And Performance ◽  
The Impact

The presented work is a result of extended research and analysis on timing methods precision, their efficiency in different virtual environments and the impact of timing precision on the performance of high-speed networks applications. We investigated how timer hardware is shared among heavily CPU- and I/O-bound tasks on a virtualized OS as well as on bare OS. By replacing the invoked timing methods within a well-known application for estimation of available path bandwidth, we provide the analysis of their impact on estimation accuracy. We show that timer overhead and precision are crucial for high-performance network applications, and low-precision timing methods usage, e.g., the delays and overheads issued by virtualization result in the degradation of the virtual environment. Furthermore, in this paper, we provide confirmation that, by using the methods we intentionally developed for both precise timing operations and AvB estimation, it is possible to overcome the inefficiency of standard time-related operations and overhead that comes with the virtualization. The impacts of negative virtualization factors were investigated in five different environments to define the most optimal virtual environment for high-speed network applications.

scholarly journals FPGA Implementation of DTCWT and PCA Based Watermarking Technique

2018 ◽  
Vol 7 (2) ◽  
pp. 82
Author(s):  
M. S. Sudha ◽  
T. C. Thanuja
Keyword(s):  
Wavelet Transform ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Implementation ◽  
Image Watermarking ◽  
Software Implementation ◽  
Low Power Consumption ◽  
Complex Wavelet Transform ◽  
System Generator ◽  
Field Programmable

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

scholarly journals A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm Using Verilog HDL

2021 ◽  
Vol 9 (VII) ◽  
pp. 1876-1879
Author(s):  
Charrith Srinivaas
Keyword(s):  
Advanced Encryption Standard ◽  
Verilog Hdl ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Rapid Pace ◽  
Tools And Techniques ◽  
Day By Day

As the technology is getting more and more advanced day by day in a rapid pace the problem for the security of data is also increasing at a very staggering rate. The hackers are equipped with new advanced tools and techniques to break any security system. Hence people are getting even more concerned about their data and data’s security. The data security can be achieved by either software or hardware implementations or both put together working in harmony. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide and have far greater more efficiency. This work mainly focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm which is the most highly used algorithm for Encryption. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and therefore the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work Mainly discusses the design implementation of the AES algorithm and the resources which are consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows- Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer.

scholarly journals DES encryption and decryption algorithm implementation based on FPGA

2020 ◽  
Vol 18 (2) ◽  
pp. 774
Author(s):  
Subhi R. M. Zeebaree
Keyword(s):  
Data Security ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
The Internet ◽  
Clock Frequency ◽  
Hardware Implementations ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Algorithm Implementation

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

NONLINEAR FM INDEX APPLICATION FOR ALIGNMENT OF SHORT DNA SEQUENCES USING RE-PARAMETRIZATION OF ALGORITHMS

Fractals ◽  
2018 ◽  
Vol 26 (03) ◽  
pp. 1850023 ◽  
Author(s):  
D. PACHECO BAUTISTA ◽  
R. CARREÑO AGUILERA ◽  
E. CORTÉS PÉREZ ◽  
M. GONZÁLEZ PÉREZ ◽  
J. J. MEDEL ◽  
...  
Keyword(s):  
Dna Sequences ◽  
Processing Speed ◽  
High Speed ◽  
Hardware Implementation ◽  
Massively Parallel Sequencing ◽  
Search Algorithm ◽  
Massively Parallel ◽  
Field Programmable ◽  
Very High ◽  
Computation Speed

An innovative reconfiguration application is proposed to re-calculate the parameters of the Ferragina and Manzini exact search algorithm (or FM indexes), using a modular and efficient hardware implementation to accelerate alignment programs of short DNA sequence reads. Although these programs use multi-core execution strategies or multiple computers, they have become slow considering the very high speed at which the new massively parallel sequencing machines produce the reads to be aligned. Consequently, a search for different ways to accelerate the alignment is crucial. The proposed design runs with software functions in a hybrid system, and has the ability to align millions of reads to reference as large as the human genome. Tests on the M505k325t card show that a single alignment core can accelerate the computation by a factor close to [Formula: see text] in relation to BWA. Due to the minor consumption of area and power, multiple alignment cores can fill the Field Programmable Gate Array (FPGA) by multiplying the computation speed. With a multiple-core implementation, the processing speed of the design outperforms applications that are accelerated by GPUs and competes with similar FPGA proposals whose cost is much higher.

Sign in / Sign up

Export Citation Format

Share Document