A low-voltage low-power fully differential rail-to-rail input/output opamp in 65-nm CMOS

2008 ◽  
Author(s):  
Weixun Yan ◽  
Robert Kolm ◽  
Horst Zimmermann
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Input Output ◽  
Fully Differential ◽  
Rail To Rail

Input–output Rail-to-Rail CMOS CCII for low voltage–low power applications

2016 ◽  
Vol 48 ◽  
pp. 60-75 ◽  
Author(s):  
Ahmed Reda ◽  
Mohamed F. Ibrahim ◽  
Fathi Farag
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Input Output ◽  
Rail To Rail

LOW VOLTAGE LOW POWER FULLY DIFFERENTIAL BUFFER

2009 ◽  
Vol 18 (03) ◽  
pp. 497-502 ◽  
Author(s):  
VINCENZO STORNELLI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Common Mode ◽  
Figures Of Merit ◽  
Fully Differential ◽  
General Performance ◽  
Rail To Rail ◽  
The Common

In this paper a useful CMOS fully-differential buffer topology is presented. The proposed solution, performing the common mode feedback operation, shows a rail-to-rail characteristic, so it is particularly suitable for low-voltage (± 0.75 V) low-power (< 400 μW) applications. The simulated results have shown excellent general performance, evaluated in terms of suitable figures of merit.

scholarly journals A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

1970 ◽  
pp. 22
Author(s):  
M.R. Valero ◽  
S. Celma ◽  
N. Medrano
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Threshold Region ◽  
Input Output ◽  
Output Stage ◽  
Common Mode ◽  
Ultra Low Power ◽  
Rail To Rail

This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

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